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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semico nductor inc. all rights reserved. features ? integrated single-chip 10/100 mbps ethernet switch ? 16 10/100 mbps autosensing, fast ethernet ports with rmii or serial interface (7ws). each port can independently use one of the two interfaces. ? serial cpu interface for configuration ? supports one frame buffer memory domain with sram at 100 mhz ? supports sram domain memory size 1 mb or 2mb ? applies centralized shared memory architecture ? up to 64 k mac addresses ? maximum throughput is 1.6 gbps non-blocking ? high performance packet forwarding (4.762 m packets per second) at full wire speed ? full duplex ethernet ieee 802.3x flow control ? backpressure flow control for half duplex ports ? supports ethernet multicasting and broadcasting and flooding control ? supports per-system option to enable flow control for best effort frames even on qos-enabled ports ? load sharing among trunked ports can be based on source mac and/or destination mac ? port mirroring to a dedicated mirroring port ? full set of led signals provided by a serial interface ? 2 port trunking groups with up to 4 10/100 ports per group ? built-in self test for internal and external sram ? traffic classification ? 4 transmission priorities for fast ethernet ports with 2 dropping levels ? classification based on: - port based priority - vlan priority field in vlan tagged frame - ds/tos field in ip packet - udp/tcp logical ports: 8 hard-wired and 8 programmable ports, including one programmable range ? the precedence of the above classifications is programmable february 2004 ordering information ZL50415/gkc 553 pin hsbga -40c to 85c figure 1 - ZL50415 system block diagram fdb interface frame data buffer a sram (1 m / 2 m) led search engine mct link frame engine fcb serial management module 16 x 10 /100 rmii ports 0 - 15 vlan 1 mct parallel / ZL50415 unmanaged 16-port 10/100 m ethernet switch data sheet
ZL50415 data sheet 2 zarlink semiconductor inc. ? qos support ? supports ieee 802.1p/q quality of service with 4 transmission priority queues with delay bounded, strict priority, and wfq service disciplines ? provides 2 levels of dropping precedence with wred mechanism ? user controls the wred thresholds ? buffer management: per class and per port buffer reservations ? port-based priority: vlan priority in a tagged frame can be overwritten by the priority of port vlan id ? hardware auto-negotiation through serial management interface (mdio) for ethernet ports ? built-in reset logic triggered by system malfunction ?i 2 c eeprom for configuration ? 553 bga package description the ZL50415 is a high density, low cost, high perform ance, non-blocking ethernet switch chip. a single chip provides 16 ports at 10/100 mbps for unmanaged switch applications. the chip supports up to 64 k mac addresses. the centraliz ed shared memory architecture permits a very high performance packet forwarding rate at up to 3.571 m packets per second at full wire speed. the chip is optimized to provide low-cost, high-performance workgroup switching. the frame buffer memory domains utilize cost-effective, high-performance synchronous sram with aggregate bandwidth of 6.4 gbps to support full wire speed on all ports simultaneously. with delay bounded, strict priority, and/or wfq tran smission scheduling, and wred dropping schemes, the ZL50415 provides powerful qos functions for various mu ltimedia and mission-critic al applications. the chip provides 4 transmission priorities and 2 levels of dr opping precedence. each packet is assigned a transmission priority and dropping precedence based on the vlan priori ty field in a vlan tagged frame, or the ds/tos field, and udp/tcp logical port fields in ip packets. the ZL50415 recognizes a total of 16 udp/tcp logical ports, 8 hard- wired and 8 programmable (including one programmable range). the ZL50415 supports 2 groups of port trunking/load shar ing. each 10/100 group can contain up to 4 ports. port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. in half-duplex mode, all ports support backpressure flow c ontrol, to minimize the risk of losing data during long activity bursts. in full-duplex mode , ieee 802.3x flow control is provided. the ZL50415 also s upports a per-system option to enable flow control for best effort frames, even on qos-enabled ports. the ZL50415 is fabricated using 0.25 micron technology. inputs, however, are 3.3 v tolerant, and the outputs are capable of directly interfacing to lvttl levels. the zl 50415 is packaged in a 553-pin ball grid array package. ZL50415 data sheet table of contents 3 zarlink semiconductor inc. 1.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 frame data buffer (fdb) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 10/100 mac module (rmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 configuration interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.6 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.7 internal memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 ZL50415 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 detailed memory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 quality of service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5 priority classification rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.6 port based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.1 fcb manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 rx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.3 rxdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 txdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.1 model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.2 four qos configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.3 delay bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ZL50415 data sheet table of contents 4 zarlink semiconductor inc. 7.4 strict priority and best effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.5 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.6 wred drop threshold management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.7 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.7.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 ZL50415 flow control basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.8.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.2 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 trunking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.0 port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1 port mirroring features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 setting registers for port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.0 gpsi (7ws) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.1 gpsi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.2 scan link and scan col interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.0 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1 led interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.2 port status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.3 led interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1 ZL50415 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.2 group 0 address mac ports group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.2.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.2.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3 group 1 address vlan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.3.1 avtcl ? vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 12.3.2 avtch ? vlan type code register hig h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3.3 pvmap00_0 ? port 00 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 12.3.4 pvmap00_1 ? port 00 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 12.3.5 pvmap00_3 ? port 00 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 12.4 port configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.4.1 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.4.2 trunk0_mode? trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.4.3 trunk1_mode ? trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.4.4 tx_age ? tx queue aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.5 group 4 address search engine group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.5.1 agetime_low ? mac address aging ti me low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.5.2 agetime_high ?mac addre ss aging time high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.5.3 se_opmode ? search engine operatio n mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.6 group 5 address buffer control/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.6.1 fcbat ? fcb aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.6.2 qosc ? qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 12.6.3 fcr ? flooding control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.6.4 avpml ? vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.6.5 avpmm ? vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 12.6.6 avpmh ? vlan priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ZL50415 data sheet table of contents 5 zarlink semiconductor inc. 12.6.7 tospml ? tos priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.6.8 tospmm ? tos priority ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.6.9 tospmh ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12.6.10 avdm ? vlan discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.6.11 tosdml ? tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 12.6.12 bmrc - broadcast/multicast rate cont rol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6.13 ucc ? unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6.14 mcc ? multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6.15 pr100 ? port reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.6.16 sfcb ? share fcb size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.6.17 c2rs ? class 2 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.6.18 c3rs ? class 3 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.6.19 c4rs ? class 4 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.6.20 c5rs ? class 5 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.6.21 c6rs ? class 6 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.6.22 c7rs ? class 7 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.6.23 classes byte limit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.6.24 classes byte limit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.6.25 classes byte limit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 12.6.26 classes byte limit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.6.27 classes wfq credit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.6.28 classes wfq credit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12.6.29 classes wfq credit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.6.30 classes wfq credit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.6.31 rdrc0 ? wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 12.6.32 rdrc1 ? wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.6.33 user defined logical ports and well known ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 12.6.33.1 user_port0_(0~7) ? user define logical port (0 ~7). . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.6.33.2 user_port_[1:0]_priority - user define logi c port 1 and 0 priority . . . . . . . . . . . . . 55 12.6.33.3 user_port_[3:2]_priority - user define logi c port 3 and 2 priority . . . . . . . . . . . . . 55 12.6.34 user_port_[5:4]_priority - user define logic port 5 and 4 priority. . . . . . . . . . . . . . . . . . 56 12.6.35 user_port_[7:6]_priority - user define logic port 7 and 6 priority. . . . . . . . . . . . . . . . . . 56 12.6.36 user_port_enable [7:0] ? user define logic 7 to 0 port enables. . . . . . . . . . . . . . . . . . . . 56 12.6.36.1 well_known_port [1:0] priority- well kn own logic port 1 and 0 priority . . . . . . 56 12.6.36.2 well_known_port [3:2] priority- well kn own logic port 3 and 2 priority . . . . . . 56 12.6.36.3 well_known_port [5:4] priority- well kn own logic port 5 and 4 priority . . . . . . 57 12.6.36.4 well_known_port [7:6] priority- well kn own logic port 7 and 6 priority . . . . . . 57 12.6.36.5 well known_port_enable [7:0] ? well known logic 7 to 0 port enables. . . . . . . . 57 12.6.36.6 rlowh ? user define range low bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.6.36.7 rhighl ? user define range high bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6.36.8 rhighh ? user define range high bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.6.36.9 rpriority ? user define range priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.7 group 6 address misc group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.7.1 mii_op0 ? mii register option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.7.2 mii_op1 ? mii register option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.7.3 fen ? feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.7.4 miic0 ? mii command register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.7.5 miic1 ? mii command register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.7.6 miic2 ? mii command register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.7.7 mic3 ? mii command register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.7.8 miid0 ? mii data register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.7.9 miid1 ? mii data register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ZL50415 data sheet table of contents 6 zarlink semiconductor inc. 12.7.10 led mode ? led control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12.7.11 checksum - eeprom ch ecksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 12.8 group 7 address port mirroring group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.8.1 mirror1_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 12.8.2 mirror1_dest ? port mirror destina tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 12.8.3 mirror2_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 12.8.4 mirror2_dest ? port mirror destina tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 12.9 group f address cpu access group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.9.1 gcr-global control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.9.2 dcr-device status and signature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 12.9.3 dcr1-chip status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.9.4 dpst ? device port status regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 12.9.5 dtst ? data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.9.6 pllcr - pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.9.6.1 lclk - la_clk delay from internal oe_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.9.7 oeclk - internal oe_clk delay from sclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 12.9.8 da ? da register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.0 bga and ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.1 bga views (top - view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.1.1 encapsulated view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.2 ball ? signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.2.1 ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13.3 ball ? signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.4 ac/dc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.1 absolute maxi mum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.4.3 recommended operating cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.4.4 typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.5 local frame buffer sbram memory inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.5.1 local sbram memory interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.6 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.6.1 reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 13.6.2 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.6.3 scanlink scancol output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 13.6.4 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 13.6.5 i2c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.6.6 serial interface setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ZL50415 data sheet list of figures 7 zarlink semiconductor inc. figure 1 - ZL50415 system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - data transfer format for i2c in terface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3 - ZL50415 sram interface block diagram (dmas for 10/ 1000 ports only) . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 - priority classification rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 - memory configuration for: 1 bank, 1 layer, 1 mb tota l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 - memory configuration for: 1 bank, 2 layer, 2 mb tota l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 - memory configuration for: 1 bank, 1 layer, 2 mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 - buffer partition scheme used to implement buffer management in the ZL50415 . . . . . . . . . . . . . . . . 26 figure 9 - gpsi (7ws) mode connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10 - scan link and scan collison status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11 - timing diagram of led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12 - typical reset & bootstrap timi ng diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 13 - local memory interface ? input setup and hold timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 14 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 15 - ac characteristics ? reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 16 - ac characteristics ? reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 17 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 18 - scanlink scancol output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 19 - scanlink, scancol setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 20 - mdio input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 21 - mdio output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 22 - i2c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 23 - i2c output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 24 - serial interface setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 25 - serial interface output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ZL50415 data sheet list of tables 8 zarlink semiconductor inc. table 1 - memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 - memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3 - supported memory configurations (pipeline sbram mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 - options for memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5 - two-dimensional world traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6 - four qos configurations for a 10/100 mbps port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7 - wred drop thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8 - mapping between ZL50415 and ietf diffserv classes for 10 /100 ports . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9 - ZL50415 features enabling ietf diffserv standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10 - reset & bootstrap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 11 - ac characteristics ? local frame buffer sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 12 - ac characteristics ? reduced me dia independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 13 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 14 - scanlink, scancol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 15 - mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 16 - i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 17 - serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ZL50415 data sheet 9 zarlink semiconductor inc. 1.0 block functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports sbram memory at 100 mhz. to ensure a non-blocking switch, one memory domain with a 64-bit wide memory bu s is required. at 100 mhz, the aggregate memory bandwidth is 6.4 gbps which is enough to support 16 10/100 mbps. the switching database is also locate d in the external sram; it is used for storing mac addresses and their physical port number. 1.2 10/100 mac module (rmac) the 10/100 media access control module provides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). th e ZL50415 has two interfaces, rmii or serial (only for 10 m). the 10/100 mac of the ZL50415 device meets the ieee 802.3 specification. it is able to operate in either half or full duplex mode with a back pr essure/flow control mechan ism. in addition, it w ill automatically retransmit upon collision for up to 16 total transmissions. the phy addr ess for 16 10/100 mac are from 08h to 17h. 1.3 configuration interface module the ZL50415 supports a serial and an i 2 c interface, which provides an easy way to configure the system. once configured, the resulting configuration can be stored in an i 2 c eeprom. 1.4 frame engine the main function of the frame engine is to forward a fram e to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, sent to the search engine to resolve the destination port. the arrivi ng frame is moved to the fdb. after receiving a switch response from the search engine, the frame engine performs transmission scheduling based on the frame?s priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.5 search engine the search engine resolves the frame?s destination port or ports according to the destination mac address (l2). it also performs mac learning, priority assignment and trunking functions. 1.6 led interface the led interface provides a serial interfac e for carrying 16 port status signals. 1.7 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contai ns the control information of the associated frame stored in the fdb, e.g., frame size, read/write pointer, transmission priority, etc. ? mct link table - the mct link table stores the link ed list of mct entries that have collisions in the external mac table. the external mac table is located in the fdb memory. note: the external mac table is located in the external ssram memory. ZL50415 data sheet 10 zarlink semiconductor inc. 2.0 system configuration 2.1 configuration mode the ZL50415 can be configured by eeprom (24c02 or compatible) via an i 2 c interface at boot time or via a synchronous serial interface during operation. 2.2 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (sda) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfer of information fr om eeprom to the switch. data transfer is 8-bit serial and bidirectional, at 50 kbps. data transfer is perform ed between master and slave ic using a request / acknowledgment style of protocol. the master ic generates the timing signals and termi nates data transfer. figure 2 depicts the data transfer format. figure 2 - data transfer format for i 2 c interface 2.2.1 start condition generated by the master (in our case, the ZL50415). the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transition of the sda line. other than in the start condition (and stop condition) , the data on the sda line must be stable during the high period of scl. the high or low state of sda can only change when scl is low. in addition, when the i 2 c bus is free both lines are high. 2.2.2 address the first byte after the start conditio n determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the first data byte make up the slave address. 2.2.3 data direction the eighth bit in the first byte after the start conditio n determines the direction (r /w) of the message. a master transmitter sets this bit to w; a ma ster receiver sets this bit to r. 2.2.4 acknowledgment like all clock pulses, the acknowledgment-related clock pu lse is generated by the master. however, the transmitter releases the sda line (high) during the acknowledgment cl ock pulse. furthermore, the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, then the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte, th en the slave transmitter must release the sda line to let the master generate the stop condition. 2.2.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb first. start slave address r/w ack data 1 (8 bits) ack data 2 ack data m ack stop ZL50415 data sheet 11 zarlink semiconductor inc. 2.2.6 stop condition generated by the master. the bus is considered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i 2 c interface serves the function of configuring the ZL50415 at boot time. the master is the ZL50415 and the slave is the eeprom memory. 2.3 synchronous serial interface the synchronous serial interface serves the function of configuring the ZL50415 not at boot time but via a pc. the pc serves as master and the ZL50415 serves as slave. the protocol for the synchronous serial interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged ZL50415 uses a synchronous serial interface to program the internal registers. to reduce the number of signals required, the register address, command and data are shifted in serially through the d0 pin. strobe- pin is used as the shift clock. autofd- pin is used as data return path. each command consists of four parts. ? start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending a abort pulse to the ZL50415. a start command is detected when d0 is sampled high when strobe- rise and d0 is sampled low when strobe- fall. an abort command is detected when d0 is sampled low when strobe- rise and d0 is sampled high when strobe- fall. 2.3.1 write command strobe- d0 a0 a2 ... a9 a10 a11 a1 w d0 d1 d2 d3 d4 d5 d6 d7 start address command data 2 extra clocks after last transfer ZL50415 data sheet 12 zarlink semiconductor inc. 2.3.2 read command all registers in ZL50415 can be modified th rough this synchronous serial interface. 3.0 ZL50415 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available becaus e of advance buffer reservations. the memory (sram) interface is a 64-bit bus co nnected to sram bank. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port?s ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from the port?s associated rxfifo into memory (frame data buffer, or fdb). once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things the source and destination mac addresses of the frame. the search engi ne places a switch respon se in the switch response queue of the frame engine when done. among other inform ation, the search engine will have resolved the destination port of the fram e and will have determined th at the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. but first, the txq manager has to decide whether or not to drop the frame, based on global fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then the txq manager links the frame?s fcb to the correct per-port- per-class txq. unicast txq?s are linked lists of transmission jobs, represented by their associated frames? fcb?s. there is one linked list for each transmission class for eac h port. there are 4 transmission classes for each of the 16 10/ 100 ports. the txq manager is responsible for scheduling transmissi on among the queues representing different classes for a port. when the port control module det ermines that there is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port using a zarl ink semiconductor scheduling algorithm. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eo f) from memory into the port?s asso ciated txfifo. afte r reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. strobe- d0 autofd- a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data ZL50415 data sheet 13 zarlink semiconductor inc. 3.2 multicast data frame forwarding after receiving the swit ch response, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utiliz ation and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so, then the frame is dropped at so me destinations but not others, and the fcb is not released. if the frame is not dropped at a partic ular destination port, then the txq manager formats an entry in the multicast queue for that port and class. mult icast queues are physical queues (unlik e the linked lists for unicast frames). there are 2 multicast queues for each of the 16 10/100 port s. the queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entr ies. there is one multicas t queue for every two priority classes. for the 10/100 ports to map the 8 transmit prio rities into 2 multicast queues, the 2 lsb are discarded. during scheduling, the txq manager treats the unicast queue and the multicast queue of the same class as one logical queue. the older head of line of the two queues is forwarded first. the port control requests a fcb release only after the eof for the multicast frame has been read by all ports to which the frame is destined. ZL50415 data sheet 14 zarlink semiconductor inc. 4.0 memory interface 4.1 overview the ZL50415 provides a 64-bit-wide sram bank with a 64-b it. each dma can read and write from the sram bank. the following figure provides an ov erview of the ZL50415 sram bank. figure 3 - ZL50415 sram interface block diagram (dmas for 10/1000 ports only) 4.2 detailed memory information because the bus for each bank is 64 bits wide, frames ar e broken into 8-byte granules, written to and read from memory. 4.3 memory requirements to support 64 k mac address, 2 mb memory is required. when vlan support is enabled, 512 entries of the mac address table are used for storing the vl an id at vlan index mapping table. up to 1 k ethernet frame buffers ar e supported and they will use 1.5 mb of memory. each frame uses 1536 bytes. the maximum system memory requirement is 2 mb. if less memory is desired, the configuration can scale down. table 1 - memory configuration table 2 - memory map memory bank frame buffer max mac address 1m 1k 32k 2m 2k 64k sram tx dma 0-7 tx dma 8-15 rx dma 0-7 rx dma 8-15 0.75 m 0.25 m 1.5 m 0.5 m 1m bank 2m bank mac address control table (mct) area frame data buffer (fdr) area ZL50415 data sheet 15 zarlink semiconductor inc. 5.0 search engine 5.1 search engine overview the ZL50415 search engine is optimized for high throughput searching with enhanced features to support: ? up to 64 k mac addresses ? 2 groups of port trunking ? traffic classification into 4 transmissi on priorities and 2 drop precedence levels ? flooding, broadcast, multicast storm control ? mac address learning and aging ? port based vlan 5.2 basic flow shortly after a frame enters the ZL50415 and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search engine. the switch request consists of th e first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the switch response queue, and the fram e engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addres ses, the transmission and discard priorities, whether the frame is unicast or multicast. requests are sent to the external sram to locate the associated entries in the external hash table. when all the information has been collected from extern al sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other t han the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, then the result is ei ther learning (s ource mac address unknown) or flooding (desti nation mac address unknown). in addition, port based vlan information is used to sele ct the correct set of destination ports for the frame (for multicast) or to verify that the frame?s destinati on port is associated with the vlan (for unicast). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be tran smitted? this is easily com puted using a hash of the source and destination mac addresses. as stated earlier, when all the information is compiled, the switch re sponse is generated. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and destina tion mac address searching. as we indicated earlier, if a match is not found, then the next entry in the link ed list must be examined and so on until a match is found or the end of the list is reached. the port based vlan bitmap is used to determine whether the frame should be forwarded to the outgoing port. when the egress port is not included in the ingress port vlan bitmap, the packet is discarded. the mac search block is also responsible for updati ng the source mac address timestamp and the vlan port association timestamp, used for aging. ZL50415 data sheet 16 zarlink semiconductor inc. 5.3.2 learning the learning module learns new mac addresses and perform s port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. learning and port change will be perform ed based on memory slot availability only. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable "age out" time interval. as we indicated earlier, the search module updates the source mac address timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table. 5.4 quality of service quality of service (qos) refers to the ability of a network to provide better se rvice to selected network traffic over various technologies. primary goals of qos include dedi cated bandwidth, controlled jitter and latency (required by some real-time and interactive traffic) and improved loss characteristics. traditional ethernet networks have had no prioritization of traffic. without a protocol to prioritize or differentiate traffic, a service level known as "best effort" attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. in a congested network or when a low-performance switch/router is overloaded, "best effort" becomes unsuit able for delay-sensitive traf fic and mission-critical data transmission. the advent of qos for packet-base d systems accommodates the integration of delay-sensitive video and multimedia traffic onto any existing ethernet network. it al so alleviates the congestion issues that have previously plagued such "best effort" networking systems. qos provid es ethernet networks with the breakthrough technology to prioritize traffic and ens ure that a certain transmission will have a guaranteed mi nimum amount of bandwidth. extensive core qos mechanisms are built into the ZL50415 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(wfq) scheduling at the egress port. in the ZL50415, qos-based policies sort traffic into a small number of classes and mark the packets accordingly. the qos identifier provides specific tr eatment to traffic in different classes so that different quality of service is provided to each class. frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. for example, the overall se rvice given to frames and packets in the premium class will be better than that given to the stan dard class; the premium cl ass is expected to experience lower loss rate or delay. the ZL50415 supports the following qos techniques: ? in a port-based setup, any station connected to the sa me physical port of the switch will have the same transmit priority. ? in a tag-based setup, a 3-bit field in the vlan tag provi des the priority of the packet. this priority can be mapped to different queues in the switch to provide qos. ? in a tos/ds-based set up, tos stands for "type of se rvice" that may include "minimize delay," "maximize throughput," or "maximize reliability." network nodes ma y select routing paths or forwarding behaviors that are suitably engineered to satisfy the service request. ? in a logical port-based set up, a logical port provides the application information of the packet. certain applications are more sensitive to delays than others; us ing logical ports to classify packets can help speed up delay sensitive applications, such as voip. ZL50415 data sheet 17 zarlink semiconductor inc. 5.5 priority classification rule figure 4 shows the ZL50415 priority classification rule. figure 4 - priority classification rule 5.6 port based vlan an administrator can use the pvmap registers to configur e the ZL50415 for port-based vlan. for example, ports 1-3 might be assigned to the marketing vlan, ports 4-6 to the engineering vlan, and ports 7-9 to the administrative vlan. the ZL50415 determines the vlan me mbership of each packet by noting the port on which it arrives. from there, the ZL50415 determines which outgo ing port(s) is/are eligible to transmit each packet or whether the packet should be discarded. for example, in the above table a 1 denotes that an outgoing port is eligib le to receive a packet from an incoming port. a 0 (zero) denotes that an outgoing port is not e ligible to receive a packet from an incoming port. destination port numbers bit map port registers 15 ... 2 1 0 register for port #0 pvmap00_0[7:0] to pvmap00_1[7:0] 0 110 register for port #1 pvmap01_0[7:0] to pvmap01_1[7:0] 0 111 register for port #2 pvmap02_0[7:0] to pvmap02_1[7:0] 0 000 ... register for port #15 pvmap15_0[7:0] to pvmap15_1[7:0] 0 000 fix port priority ? yes yes yes yes yes yes no no no no no use tos use logical port use default port settings use vlan priority use default port settings tos precedence over vlan? vlan tag ? ip frame ? ip (fcr register, bit 7) no use logical port ZL50415 data sheet 18 zarlink semiconductor inc. in this example: ? data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. ? data packets received at port #1 are eligible to be sent to outgoing ports 0, and 2. ? data packets received at port #2 are not eligible to be sent to ports 0 and 1. 5.7 memory configurations the ZL50415 supports the following memory configurations. . it supports 1 m and 2 m configurations. table 3 - supported memory configurations (pipeline sbram mode) table 4 - options for memory configuration configuration 1 m (bootstrap pin tstout7 = open) 2m (bootstrap pin tstout7 = pull down) connections single layer (bootstrap pin tstout13 = open) two 128 k x 32 sram/bank or one 128 k x 64 sram/bank two 256 k x 32 sram/bank connect 0e# and we# double layer (bootstrap pin tstout13 = pull down) na four 128 k x 32 sram/bank or two 128 k x 64 sram/bank connect 0e0# and we0# connect 0e1# and we1# frame data buffer only bank a bank a and bank b 1m (sram) 2m (sram) 1m/bank (sram) 2m/bank (sram) ZL50415 xx zl50416 xx zl50417 xx zl50418 xx ZL50415 data sheet 19 zarlink semiconductor inc. figure 5 - memory configuration for: 1 bank, 1 layer, 1 mb total figure 6 - memory configuration for: 1 bank, 2 layer, 2 mb total memory 128 k 32 bits sram memory 128 k 32 bits data la_d[63:32] data la_d[31:0] address la_a[19:3] bank a (1 m one layer) bootstraps: tstout7 = open, ts tout13 = open, tstout4 = open sram memory 128 k 32 bits data la_d[63:32] data la_d[31:0] bank a (2 m two layers) sram memory 128 k 32 bits address la_a[19:3] sram memory 128 k 32 bits sram memory 128 k 32 bits bootstraps: tstout7 = pull down, tstout13 = pull down, tstout4 = open ZL50415 data sheet 20 zarlink semiconductor inc. figure 7 - memory configuration for: 1 bank, 1 layer, 2 mb 6.0 frame engine 6.1 data forwarding summary when a frame enters the de vice at the rxmac, the rxdma will move th e data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjun ction with the scheme for the sram interface. a switch request is sent to the search engine. the search engine processes the switch request. a switch response is sent back to the frame engine and in dicates whether the frame is unicast or multicast, and its destination port or ports. a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling reque st, the device will format an entry in t he appropriate transm ission scheduling queue (txsch q) or queues. there are 4 txsch q for eac h 10/100, one for each priority. creation of a queue entry either involves linking a new job to the appropriate lin ked list if unicast, or adding an entry to a physical queue if multicast. when the port is ready to accept the next frame, the txq manager will get the head-of -line (hol) en try of one of the txsch qs, according to the transmission scheduling al gorithm (so as to ensure per-class quality of service). the unicast linked list and the multicast queue for the same port-class pa ir are treated as one logical queue. the older hol between the two queues goes first. for 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated with unicast queue 2. the txdma will pull frame data from the memory and forward it granule-by-g ranule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the ZL50415 frame engine. memory 256 k 32 bits sram memory 256 k 32 bits data la_d[63:32] data la_d[31:0] address la_a[20:3] bank a (2 m one layer) bootstraps: tstout7 = pull down, tstout13 = open, tstout4 = open ZL50415 data sheet 21 zarlink semiconductor inc. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buffe r reservations and limits. the default values can be determined by referring to chapter 8. in addition, the fc b manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct txsch q. the buf fer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat. 6.2.2 rx interface the rx interface is mainly responsi ble for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an e nd of frame that is good the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per-c lass queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receivin g a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame?s fcb to the correct per-port-per-class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for the incoming frame?s so urce if that port is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read addres s for the frame currently being transmitted. it also writes start of frame information and an end of frame flag to th e mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control and arbitrates among buffer release requests from the port control modules. 7.0 quality of se rvice and flow control 7.1 model quality of service is an all-encompassi ng term for which different people have different interpretations. in general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. we also assume that the incoming traffic is not policed or sh aped. furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. the manager can then subdivide the applications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offered to the switch. as an added bonus, although we do not assume an ything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide additional assurances about our switch?s performance. ZL50415 data sheet 22 zarlink semiconductor inc. table 6 shows examples of qos applications with three transm ission priorities, but best effort (p0) traffic may form a fourth class with no bandwidth or latency assurances. table 5 - two-dimensional world traffic a class is capable of offering traffic that exceeds the co ntracted bandwidth. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a misbehaving class offers tr affic that exceeds the agreed- upon rate. a misbehaving class is formed from an aggr egation of misbehaving microflows. to achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. however, such le niency must not degrade the quality of service (qos) rece ived by well-behaved classes. as table 6 illustrates, the six traffic types may each have their own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the ta ble, p3, the highest transmission class, requires that all frames be transmitted within 1 ms and receives 50% of the 100 mbps of bandwidth at that port. best-effort (p0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. it is also possible to add a fourth class that has strict priority over the other three; if this class has even one frame to transmit, t hen it goes first. in the ZL50415, each 10/100 mbps port will support four total classes, and each 1000 mbps port will support eight classes. we will discuss the various modes of sch eduling these classes in the next section. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should rarely lose packets. but poorly behaved user s ? users who send frames at too high a rate ? will encounter frame loss and the first to be discarded will be high-drop. of course, if this is insufficient to resolve the congestion, eventually some low-drop frames are dropped and then all frames in the worst case. table 6 shows that different types of applications may be pl aced in different boxes in the traffic table. for example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas voip fits into the category of low-loss , low-latency traffic. goals to ta l assured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) highest transmission priority, p3 50 mbps apps: phone calls, circuit emulation. latency: < 1 ms. drop: no drop if p3 not oversubscribed. apps: training video. latency: < 1 ms. drop: no drop if p3 not oversubscribed; first p3 to drop otherwise. middle transmission priority, p2 37.5 mbps apps: interactive apps, web business. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed. apps: non-critical interactive apps. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed; firstp2 to drop otherwise. low transmission priority, p1 12.5 mbps apps: emails, file backups. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed. apps: casual web browsing. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed; first to drop otherwise. to ta l 1 0 0 m b p s ZL50415 data sheet 23 zarlink semiconductor inc. 7.2 four qos configurations there are four basic pieces to qos scheduling in the zl 50415: strict priority (sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four piec es, there are four different modes of operation, as shown in table and table 6. for 10/100 mbps ports, thes e modes are selected by the following registers: table 6 - four qos configurations for a 10/100 mbps port the default configuration for a 10/100 mbps port is three delay-bounded queues and one best-effort queue. the delay bounds per class are 0.8 ms for p3, 2 ms for p2, and 12.8 ms for p1. best effort traffic is only served when there is no delay-bounded traffic to be served. we have a second configuration for a 10/100 mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. the delay bo unds per class are 3.2 ms for p2 and 12.8 ms for p1. if the user is to choose this configuratio n, it is important that p3 (sp) traffic be either policed or implicitly bounded (e.g., if the incoming p3 traffic is very light and predic tably patterned). strict priority traffic, if not admission- controlled at a prior stage to the ZL50415, can have a de leterious effect on all other classes? performance. the third configuration for a 10/100 mbps port contains one strict priority queue and three queues receiving a bandwidth partition via wfq. as in the se cond configuration, strict priority traf fic needs to be carefully controlled. in the fourth configuration, all queues ar e served using a wfq service discipline. 7.3 delay bound in the absence of a sophisticated qos server and si gnaling protocol, the ZL50415 may not know the mix of incoming traffic ahead of time. to cope with this uncertai nty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (hol) frames. as a result, we assure latency bounds for all admit ted frames with high confidenc e, even in the presence of system-wide congestion. our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. our algorithm also di fferentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random ear ly dropping prevents conges tion by randomly dropping a percentage of high-drop fram es even before the chip?s buffers are comp letely full, while st ill largely sparing low- drop frames. this allows high-drop frames to be discarded early, as a sacrifice for futu re low-drop frames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. qosc24 [7:6] credit_c00 qosc28 [7:6] credit_c10 qosc32 [7:6] credit_c20 qosc36 [7:6] credit_c30 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq ZL50415 data sheet 24 zarlink semiconductor inc. 7.4 strict priority and best effort when strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of our four qos configurations include st rict priority queues. the goal is for stri ct priority classes to be used for ietf expedited forwarding (ef), where performance guarantees are required. as we have indicated, it is important that strict priority traffic be either policed or implicitly b ounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos conf igurations include best effort queues. the goal is for best effort classes to be used for non-esse ntial traffic, because we provide no as surances about best effort performance. however, in a typical network settin g, much best effort traffic will indeed be transmitted and with an adequate degree of expediency. because we do not provide any delay assurances for best ef fort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50415, we do not enforce a fair bandwidth partition by dr opping strict priority traffic. to summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. we only drop frames from best effort and strict priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments ? for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essent ial, wfq may be preferable to a delay-bounded scheduling discipline. the ZL50415 provides the us er with a wfq option with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. the user sets four wfq ?weights? such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the ZL50415 still retains a set of dropping rules that helps to prevent congestion and trigger higher le vel protocol end-to-end flow control. as before, when strict priori ty is combined with wfq, we do not have sp ecial dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, we do indeed drop frames from sp queues for global buffer management purposes. in addition, queue p0 for a 10/100 port are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a wfq scheduling perspective. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summarizes the behavior of the wred logic. table 7 - wred drop thresholds px is the total byte count, in the priority queue x. the wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the prio rity queues. if delay bound scheduling is used, n equals in kb (kilobytes) p3 p2 p1 high drop low drop level 1 n 120 p3 akb p2 bkb p1 ckb x% 0% level 2 n 140 y% z% level 3 n 160 100% 100% ZL50415 data sheet 25 zarlink semiconductor inc. p3*16+p2*4+p1. if using wfq scheduling, n equals p3+p 2+p1. each drop level from one to three has defined high-drop and low-drop percentages, which indicate the minimum and maximum percentages of the data that can be discarded. the x, y z percent c an be programmed by the register rdrc0, rdrc1. in level 3, all packets are dropped if the bytes in each priority queue exceed the threshold. parameters a, b, c are the byte count thresholds for each priority queue. they can be programmed by the qos control register (refer to the register group 5.) see programming qos registers application note for more information. 7.7 buffer management because the number of fdb slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a we ll-behaved source port or class, we introduce the concept of buffer management into the ZL50415. our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in figure 8 on page 26. as shown in the figure, the fdb pool is divided into se veral parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temp orary region is necessary, because when the frame first enters the ZL50415, its destination port and class are as yet unknown and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame ca n be received first before subjecting them to the frame drop discipline after classifying. six reserved sections, one for each of the first six prio rity classes, ensure a progra mmable number of fdb slots per class. the lowest two classes do not receive any buffer reservation. furthermore, even for 10/100 mbps ports, a frame is stored in the region of the fdb corresponding to its class. as we have indicated, the eight classes use only four transmission scheduling queues for 10/100 mbps ports but as far as buffer usage is concerned, there are still eight distinguishable classes. another segment of the fdb reserves space for each of th e 24 regions. one parameters can be set for the source port reservation for 10/100 mbps. these 16 reserved regions make sure that no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool, wh ich can store any type of frame. the frame engine allocates the frames first in the six priority sections. when the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. once the shared poll is full the frames are allocated in the section reserved for the source port. the following registers define the size of each section of the frame data buffer: pr100- port reservation for 10/100 ports sfcb- share fcb size c2rs- class 2 reserve size c3rs- class 3 reserve size c4rs- class 4 reserve size c5rs- class 5 reserve size c6rs- class 6 reserve size c7rs- class 7 reserve size ZL50415 data sheet 26 zarlink semiconductor inc. figure 8 - buffer partition scheme used to implement buffer management in the ZL50415 7.7.1 dropping when buffers are scarce summarizing the two examples of local dr opping discussed earlier in this chapter: ? if a queue is a delay-bounded queue, we have a multilev el wred drop scheme, designed to control delay and partition bandwidth in case of congestion. ? if a queue is a wfq-scheduled queue, we have a mult ilevel wred drop scheme, designed to prevent congestion. in addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. the function of buffer management is to make sure that such dropping ca uses as little blocking as possible. 7.8 ZL50415 flow control basics because frame loss is unacceptable for some applications , the ZL50415 provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch ma y trigger a flow control signal; this signal tells a source port that is sending a packet to th is switch, to temporarily hold off. while flow control offers the clear benefit of no packet loss , it also introduces a problem for quality of service. when a source port receives an ethernet fl ow control signal, all microflows origi nating at that port, well-behaved or not, are halted. a single packet destined for a congested ou tput can block other packet s destined for uncongested outputs. the resulting head-of-line bl ocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the ZL50415, each source port can independently have flow control enabled or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames fr om flow control enabled ports feed to shared pool per-source reservations (24 10/100 m, cpu) temporary reservation per-class reservation ZL50415 data sheet 27 zarlink semiconductor inc. only one queue at the destination, the qu eue of lowest priority. what this means is that if flow control is enabled for a given source port, then we ca n guarantee that no packets originating from that port will be lo st, but at the possible expense of minimum bandwidth or maximum delay assura nces. in addition, these "d owngraded" frames may only use the shared pool or the per-source reserved pool in the fdb; frames from flow control enabled sources may not use reserved fdb slots for the highest six classes (p2-p7). the ZL50415 does provide a syst em-wide option of permittin g normal qos scheduling (a nd buffer use) for frames originating from flow control enabled ports. when this programmable option is active, it is possible that some packets may be dropped, even though flow control is on. the reason is that intelligent packet dropping is a major component of the ZL50415?s approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.8.1 unicast flow control for unicast frames, flow control is trig gered by source po rt resource availability. re call that the ZL50415?s buffer management scheme allocates a reserved number of fdb slots for each source port. if a programmed number of a source port?s reserved fdb slots have been used, then flow control xoff is triggered. xon is triggered when a port is currently being flow controlled and all of that port?s reserved fdb slots have been released. note that the ZL50415?s per-source-port fdb reservations a ssure that a source port that sends a single frame to a congested destination will no t be flow controlled. 7.8.2 multicast flow control in unmanaged mode, flow control for mu lticast frames is triggered by a gl obal buffer counter. when the system exceeds a programmable threshold of multicast packets, xoff is triggered. xon is triggered when the system returns below this threshold. in addition, each source port has a 15-bit port map reco rding which port or ports of the multicast frame?s fanout were congested at the time xoff was triggered. all ports are continuously monitored for congestion, and a port is identified as uncongested when its que ue occupancy falls below a fixed thres hold. when all those ports that were originally marked as congested in the port map have become uncongested, then xon is triggered, and the 15-bit vector is reset to zero. 7.9 mapping to ietf diffserv classes for 10/100 mbps ports, the classes of table 8 are merged in pairs?one class corresponding to nm+ef, two af classes, and a single be class. table 8 - mapping between ZL50415 and ietf diffserv classes for 10/100 ports features of the ZL50415 that correspond to the requir ements of their associated ietf classes are summarized in the table below. zl p3 p2 p1 p0 ietf nm+ef af0 af1 be0 network management (nm) and expedited forwarding (ef) ? global buffer reservation for nm and ef ? option of strict priority scheduling ? no dropping if admission controlled ZL50415 data sheet 28 zarlink semiconductor inc. table 9 - ZL50415 features enabling ietf diffserv standards 8.0 port trunking 8.1 features and restrictions ? a port group (i.e., trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same ZL50415. ? load distribution among the ports in a trunk for uni cast is performed using hashing based on source mac address and destination mac address. three other options include source mac address only, destination mac address only, and source port (in bidirectional ring mode only). load distri bution for multicast is performed similarly. ? the ZL50415 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the ZL50415 will automatically re distribute the traffic over to the remaining ports in the trunk 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved instead of the port number. in addition, if the source address belongs to a trunk, then the source port?s trunk membership register is checked. a hash key, based on some combination of the source and destination mac addresses for the current packet, selects the appropriate forwarding port. 8.3 multicast packet forwarding for multicast packet forwarding, the de vice must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multic ast packets to the appropriate destination ports in a port trunking environment. determining one forwarding port per group. for multicast pa ckets, all but one port per group, the forwarding port, must be excluded. preventing the multicast packet from looping back to the source trunk. the search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the prim ary forwarding port for each group, we do not take the source port into account. to prevent this, we simply apply on e additional filter, so as to block that forwarding port for this multicast packet. assured forwarding (af) ? programmable bandwidth partition, with option of wfq service ? option of delay-bounded service keeps delay under fixed levels even if not admission-controlled ? random early discard, with programmable levels ? global buffer reservation for each af class best effort (be) ? service only when other queues are idle means that qos not adversely affected ? random early discard, with programmable levels ? traffic from flow control enabled ports automatically classified as be ZL50415 data sheet 29 zarlink semiconductor inc. 8.4 trunking 2 trunk groups are supported. groups 0 and 1 can trunk up to 4 10/100 ports. the supported combinations are shown in the following table. select via trunk0_mode register select via trunk1_mode register the trunks are individua lly enabled/disabled by controlling pin trunk 0,1. 9.0 port mirroring 9.1 port mirroring features the received or transmitted data of any 10/100 port in the ZL50415 chip can be "mirrored" to any other port. we support two such mirrored source-destination pairs. a mirror port cannot also serve as a data port. 9.2 setting registers for port mirroring ? mirror1_src: sets the source port for the first port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirr oring (which is the default se tting). bit [5] is used to select between ingress (rx) or egress (tx) data. ? mirror1_dest: sets the destination port for the first port mirroring pair. bits [4:0] select the destination port to be mirrored. ? mirror2_src: sets the source port for the second port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. ? mirror2_dest: sets the destination port for the se cond port mirroring pair. bits [4:0] select the destination port to be mirrored. the default is port 0. refer to port mirroring applicat ion notes for further information. group 0 port 0 port 1 port 2 port 3 group 1 port 4 port 5 port 6 port 7 ZL50415 data sheet 30 zarlink semiconductor inc. 10.0 gpsi (7ws) interface 10.1 gpsi connection the 10/100 rmii ethernet port can function in gpsi (7ws) mode when the corresponding txen pin is strapped low with a 1 k pull down resistor. in th is mode, the txd[0], txd[1], rxd[0] and rxd[1] serve as tx data, tx clock, rx data and rx clock respectively. the link status and collision from the phy are mult iplexed and shifted into the switch device through external glue logic. the dupl ex of the port can be controlled by programming the ecr register. the gpsi interface can be operated in port based vlan mode only. figure 9 - gpsi (7ws) mode connection diagram crs_dv rxd[0] rxd[1] txd[1] txd[0] txen port 0 ethernet phy 260x scan_col scan_clk scan_link ethernet port 15 ethernet phy ethernet link serializer (cpld) collision serializer (cpld) crs rxd rx_clk tx_clk txd txen link0 col0 link1 col1 link2 col2 link15 col15 ZL50415 data sheet 31 zarlink semiconductor inc. 10.2 scan link and scan col interface an external cpld logic is required to take the link signals and collision sign als from the gpsi phys and shift them into the switch device. the switch devi ce will drive out a signature to indicate the start of the seq uence. after that, the cpld should shift in the link and collision status of the phys as shown in the figure. the extra link status indicates the polarity of the link signal. one indica tes the polarity of the link signal is active high. figure 10 - scan link and sc an collison status diagram 11.0 led interface 11.1 led interface introduction a serial output channel provides port status information fr om the ZL50415 chips. it requires three additional pins. ? led_clk at 12.5 mhz ? led_syn a sync pulse that defines the boundary between status frames ? led_data a continuous serial stream of data for all status leds that repeats once every frame time a low cost external device (44 pin pal) is used to decode the serial data and to drive an led array for display. this device can be customized for different needs. 11.2 port status in the ZL50415, each port has 8 status indicators, each re presented by a single bit. the 8 led status indicators are: ? bit 0: flow control ? bit 1:transmit data ? bit 2: receive data ? bit 3: activity (where activity includes either transmission or reception of data) ? bit 4: link up ? bit 5: speed (1= 100 mb/s; 0= 10 mb/s) ? bit 6: full-duplex ? bit 7: collision eight clocks are required to cycle through the eight status bits for each port. scan_clk scan_link/ scan_col drived by vtx260x drived by cpld 25 cycles for link/ 24 cycles for col total 32 cycles period driven by zl5041x driven by cpld ZL50415 data sheet 32 zarlink semiconductor inc. when the led_syn pulse is asserted , the led interface will present 256 led clock cycl es with the clock cycles providing information fo r the following ports. port 0 (10/100): cycles #0 to cycle #7 port 1 (10/100): cycles#8 to cycle #15 port 2 (10/100): cycle #16 to cycle #23 ... port 14 (10/100): cycle #112 to cycle #119 port 15 (10/100): cycle #120 to cycle #127 reserved: cycle #128 to cycle #207 byte 26 (additional status): cycle #208 to cycle #215 byte 27 (additional status): cycle #216 to cycle #223 cycles #224 to 256 present data with a value of zero. byte 26 and byte 27 provides bist status ? 26[1:0] : reserved ? 26[2]: initialization done ? 26[3]: initialization start ? 26[4]: checksum ok ? 26[5]: link_init_complete ? 26[6]: bist_fail ? 26[7]: ram_error ? 27[0]: bist_in_process ? 27[1]: bist_done 11.3 led interface timing diagram the signal from the ZL50415 to the led decoder is shown in figure 11. figure 11 - timing diagram of led interface ZL50415 data sheet 33 zarlink semiconductor inc. 12.0 regist er definition 12.1 ZL50415 register description register description cpu addr (hex) r/w i 2 c addr (hex) default notes 0. ethernet port control registers substitute [n] with port number (0..f) ecr1p"n" port control register 1 for port n 000 + 2 x n r/w 000-018 020 ecr2p"n" port control register 2 for port n 001 + 2 x n r/w 01b-033 000 1. vlan control registers substitute [n] with port number (0..f) avtcl vlan type code register low 100 r/w 036 000 avtch vlan type code register high 101 r/w 037 081 pvmap"n"_0 port "n" configuration register 0 102 + 4n r/w 038-050 0ff pvmap"n"_1 port "n" configuration register 1 103 + 4n r/w 053-06b 0ff pvmap"n"_3 port "n" configuration register 3 105 + 4n r/w 089-0a1 007 pvmode vlan operating mode 170 r/w 0a4 000 2. trunk cont rol registers trunk0_ mode trunk group 0 mode 203 r/w 0a5 003 trunk1_ mode trunk group 1 mode 20b r/w 0a6 003 3. cpu port configuration tx_age transmission queue aging time 325 r/w 0a7 008 4. search engine configurations agetime_low mac address aging time low 400 r/w 0a8 2m:05c / 4m:02e agetime_ high mac address ag ing time high 401 r/w 0a9 000 se_opmode search engine operating mode 403 r/w na 000 5. buffer control and qos control fcbat fcb aging timer 500 r/w 0aa 0ff qosc qos control 501 r/w 0ab 000 fcr flooding control register 502 r/w 0ac 008 avpml vlan priority map low 503 r/w 0ad 000 avpmm vlan priority map middle 504 r/w 0ae 000 avpmh vlan priority map high 505 r/w 0af 000 tospml tos priority map low 506 r/w 0b0 000 ZL50415 data sheet 34 zarlink semiconductor inc. tospmm tos priority map middle 507 r/w 0b1 000 tospmh tos priority map high 508 r/w 0b2 000 avdm vlan discard map 509 r/w 0b3 000 tosdml tos discard map 50a r/w 0b4 000 bmrc broadcast/multicast rate control 50b r/w 0b5 000 ucc unicast congestion control 50c r/w 0b6 1m:008 / 2m:010 mcc multicast congesti on control 50d r/w 0b7 050 pr100 port reservation for 10/100 ports 50e r/w 0b8 1m:035 / 2m:058 sfcb share fcb size 510 r/w 0ba 1m:046 / 2m:0e6 c2rs class 2 reserve size 511 r/w 0bb 000 c3rs class 3 reserve size 512 r/w 0bc 000 c4rs class 4 reserve size 513 r/w 0bd 000 c5rs class 5 reserve size 514 r/w 0be 000 c6rs class 6 reserve size 515 r/w 0bf 000 c7rs class 7 reserve size 516 r/w 0c0 000 qosc"n" qos control (n=0 - 5) 517- 51c r/w 0c1-0c6 000 qos control (n=6 - 11) 51d- 522 r/w na 000 qos control (n=12 - 23) 523- 52e r/w 0c7-0d2 000 qos control (n=24 - 59) 52f- 552 r/w na 000 qosc"n" qos control (n=0 59) 517 512 r/w 0c1-0d2 000 rdrc0 wred drop rate control 0 553 r/w 0fb 08f rdrc1 wred drop rate control 1 554 r/w 0fc 088 user_ port"n"_low user define logical port "n" low (n=0-7) 580 + 2n r/w 0d6- 0dd 000 user_ port"n"_high user define logical port "n" high 581 + 2n r/w 0de- 0e5 000 user_ port1:0_ priority user define logic port 1 and 0 priority 590 r/w 0e6 000 register description cpu addr (hex) r/w i 2 c addr (hex) default notes ZL50415 data sheet 35 zarlink semiconductor inc. user_ port3:2_ priority user define logic port 3 and 2 priority 591 r/w 0e7 000 user_ port5:4_ priority user define logic port 5 and 4 priority 592 r/w 0e8 000 user_ port7:6_pri ority user define logic port 7 and 6 priority 593 r/w 0e9 000 user_port_ enable user define logic port enable 594 r/w 0ea 000 wlpp10 well known logic port priority for 1 and 0 595 r/w 0eb 000 wlpp32 well known logic port priority for 3 and 2 596 r/w 0ec 000 wlpp54 well known logic port priority for 5 and 4 597 r/w 0ed 000 wlpp76 well-known logic port priority for 7 & 6 598 r/w 0ee 000 wlpe well known logic port enable 599 r/w 0ef 000 rlowl user define range low bit 7:0 59a r/w 0f4 000 rlowh user define range low bit 15:8 59b r/w 0f5 000 rhighl user define range high bit 7:0 59c r/w 0d3 000 rhighh user define range high bit 15:8 59d r/w 0d4 000 rpriority user define ra nge priority 59e r/w 0d5 000 6. misc configuration registers mii_op0 mii register option 0 600 r/w 0f0 000 mii_op1 mii register option 1 601 r/w 0f1 000 fen feature registers 602 r/w 0f2 010 miic0 mii command register 0 603 r/w n/a 000 miic1 mii command register 1 604 r/w n/a 000 miic2 mii command register 2 605 r/w n/a 000 miic3 mii command register 3 606 r/w n/a 000 miid0 mii data register 0 607 ro n/a n/a miid1 mii data register 1 608 ro n/a n/a led led control register 609 r/w 0f3 000 register description cpu addr (hex) r/w i 2 c addr (hex) default notes ZL50415 data sheet 36 zarlink semiconductor inc. 12.2 group 0 address mac ports group 12.2.1 ecr1pn: po rt n control register ?i 2 c address 000-018; cpu address:0000+2xn (n = port number) ? accessed by serial interface and i 2 c (r/w) sum eeprom checksum register 60b r/w 0ff 000 7. port mirroring controls mirror1_src port mirror 1 source port 700 r/w n/a 07f mirror1_ dest port mirror 1 destination port 701 r/w n/a 017 mirror2_src port mirror 2 source port 702 r/w n/a 0ff mirror2_ dest port mirror 2 destination port 703 r/w n/a 000 f. device configuration register gcr global control register f00 r/w n/a 000 dcr device status and signature register f01 ro n/a n/a dcr1 chip status f02 ro n/a n/a dpst device port status register f03 r/w n/a 000 dtst data read back register f04 ro n/a n/a da da register fff ro n/a da 765 4321 0 sp state a-fc port mode register description cpu addr (hex) r/w i 2 c addr (hex) default notes ZL50415 data sheet 37 zarlink semiconductor inc. bit [0] ? 1 - flow control off ? 0 - flow control on ? when flow control on: ? in half duplex mode, the mac transmitter applies back pressure for flow control. ? in full duplex mode, the mac transmi tter sends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control is received. ? when flow control off: ? in half duplex mode, the mac transmitter does not assert flow control by sending flow control frames or jamming collision. ? in full duplex mode, the mac transmitt er does not send flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame received counter is not incremented. bit [1] ? 1 - half duplex - only 10/100 mode ? 0 - full duplex bit [2] ? 1 - 10 mbps ? 0 - 100 mbps bit [4:3] ? 00 - automatic enable auto neg. this enables hardware state machine for auto-negotiation. ? 01 - limited disable auto neg. th is disables hardware for speed auto- negotiation. poll mii for link status. ? 10 - link down. disable auto neg. state machine and force link down (disable the port) ? 11 - link up. user erc1 [2:0] for config. bit [5] ? asymmetric flow control enable ? 0 - disable asymmetric flow control ? 1 - enable asymmetric flow control ? asymmetric flow control enable. when th is bit is set and flow control is on (bit [0] = 0, don't send out a flow cont rol frame. but mac receiver interprets and process flow control frames. default is 0 bit [7:6] ? ss - spanning tree state default is 11 ? 00 ? blocking: frame is dropped ? 01 - listening: frame is dropped ? 10 - learning: frame is dropped. source mac address is learned. ? 11 - forwarding: frame is forwarded. source mac address is learned. ZL50415 data sheet 38 zarlink semiconductor inc. 12.2.2 ecr2pn: po rt n control register ?i 2 c address: 01b-035; cpu address:0001+2xn ? accessed by and serial interface and i 2 c (r/w) 12.3 group 1 address vlan group 12.3.1 avtcl ? vlan type code register low ?i 2 c address 036; cpu address:h100 ? accessed by serial interface and i 2 c (r/w) 7654 3 2 10 qos sel reserve disl ftf futf bit [0]: ? filter untagged frame (default 0) ?0: disable ? 1: all untagged frames from this port are discarded bit [1]: ? filter tag frame (default 0) ?0: disable ? 1: all tagged frames from this port are discarded bit [2]: ? learning disable (default 0) ? 1 learning is disabled on this port ? 0 learning is enabled on this port bit [3]: ? must be set to ?1? bit [5:4:] ? qos mode selection (default 00) ? determines which of the 4 sets of qos settings is used for 10/100 ports. ? note that there are 4 sets of per-queue byte thresholds, and 4 sets of wfq ratios programmed. these bits select among the 4 choices for each 10/100 port. refer to qos application note. ? 00: select class byte limit set 0 and classes wfq credit set 0 ? 01: select class byte limit set 1 and classes wfq credit set 1 ? 10: select class byte limit set 2 and classes wfq credit set 2 ? 11: select class byte limit set 3 and classes wfq credit set 3 bit [7:6] ? reserved bit [7:0]: ? vlantype_low: lower 8 bits of the vlan type code (default 00) ZL50415 data sheet 39 zarlink semiconductor inc. 12.3.2 avtch ? vlan type code register high ?i 2 c address 037; cpu address:h101 ? accessed by serial interface and i 2 c (r/w) 12.3.3 pvmap00_0 ? port 00 configuration register 0 ?i 2 c address 038, cpu address:h102) ? accessed by serial interface and i 2 c (r/w) this register indicates the legal egress ports. a "1" on bit 7 means that the packet can be sent to port 7. a "0" on bit 7 means that any packet destined to port 7 will be discard ed. this register works with registers 1 to form a 16 bit mask to all egress ports. 12.3.4 pvmap00_1 ? port 00 configuration register 1 ?i 2 c address h53, cpu address:h103 ? accessed by serial interface and i 2 c (r/w) 12.3.5 pvmap00_3 ? port 00 configuration register 3 ?i 2 c address h89, cpu address:h105) ? accessed by serial interface and i 2 c (r/w) bit [7:0]: ? vlantype_high: upper 8 bits of the vlan type code (default is 81) bit [7:0]: ? vlan mask for ports 7 to 0 (default ff) bit [7:0]: ? vlan mask for ports 15 to 8 (default is ff) 765 32 0 fp en drop default tx priority bit [2:0]: reserved (default 7) bit [5:3]: default transmit priority. used when bit [7] = 1 (default 0) ? 000 transmit priority level 0 (lowest) ? 001 transmit priority level 1 ? 010 transmit priority level 2 ? 011 transmit priority level 3 ? 100 transmit priority level 4 ? 101 transmit priority level 5 ? 110 transmit priority level 6 ? 111 transmit priority level 7 (highest) ZL50415 data sheet 40 zarlink semiconductor inc. 12.4 port configuration register ? pvmap01_0,1,3 i 2 c address h39,54,8a; cpu address:h106, 107,109 ? pvmap02_0,1,3 i 2 c address h3a,55,8b; cpu address:h10a, 10b, 10d ? pvmap03_0,1,3 i 2 c address h3b,56,8c; cpu address:h10e, 10f, 111 ? pvmap04_0,1,3 i 2 c address h3c,57,8d; cpu address:h112, 113, 115 ? pvmap05_0,1,3 i 2 c address h3d,58,8e; cpu address:h116, 117, 119 ? pvmap06_0,1,3 i 2 c address h3e,59,8f; cpu address:h11a, 11b, 11d ? pvmap07_0,1,3 i 2 c address h3f,5a,90; cpu address:h11e, 11f, 121 ? pvmap08_0,1,3 i 2 c address h40,5b,91; cpu address:h122, 123, 125 ? pvmap09_0,1,3 i 2 c address h41,5c,92; cpu address:h126, 127, 129 ? pvmap10_0,1,3 i 2 c address h42,5d,93; cpu address:h12a, 12b, 12d ? pvmap11_0,1,3 i 2 c address h43,5e,94; cpu address:h12e, 12f, 131 ? pvmap12_0,1,3 i 2 c address h44,5f,95; cpu address:h132, 133, 135 ? pvmap13_0,1,3 i 2 c address h45,60,96; cpu address:h136, 137, 139 ? pvmap14_0,1,3 i 2 c address h46,61,97; cpu address:h13a, 13b, 13d ? pvmap15_0,1,3 i 2 c address h47,62,98; cpu address:h13e, 13f, 141 12.4.1 pvmode ?i 2 c address: h0a4, cpu address:h170 ? accessed by serial interface, and i 2 c (r/w) bit [6]: default discard priority (default 0) ? 0 ? discard priority level 0 (lowest) ? 1 ? discard priority level 7(highest) bit [7]: enable fix priority (default 0) ?0 disable fix priority. all frames are analyzed. transmit priority and discard priority are based on vlan tag, tos field or logical port. ? 1 transmit priority and discard priority are based on values programmed in bit [6:3] 7 54 3210 sm0 df sl bit [0]: ? reserved ? must be ?0? bit [1]: ? slow learning ? same function as se_op mode bit 7. either bit can enable the function; both need to be turned off to disable the feature. ZL50415 data sheet 41 zarlink semiconductor inc. 12.4.2 trunk0_mode? trunk group 0 mode ?i 2 c address h0a5; cpu address:203 ? accessed by serial interface and i 2 c (r/w) 12.4.3 trunk1_mode ? trunk group 1 mode ?i 2 c address h0a6; cpu address:20b ? accessed by serial interface and i 2 c (r/w) bit [2]: ? disable dropping of frames with destination mac addresses 0180c2000001 to 0180c200000f (default = 0) ? 0: drop all frames in this range ? 1: disable dropping of frames in this range bit [3]: ? reserved bit [4]: ? support mac address 0 ? 0: mac address 0 is not learned. ? 1: mac address 0 is learned. bit [7:5]: ? reserved 743210 hash select port select bit [1:0]: ? port selection in unmanaged mode. input pin trunk0 enable/disable trunk group 0. ?00 reserved ? 01 port 0 and 1 are used for trunk0 ? 10 port 0, 1 and 2 are used for trunk0 ? 11 port 0, 1, 2 and 3 are used for trunk0 bit [3:2] ? hash select. the hash selected is valid for trunk 0, 1 and 2. (default 00) ? 00 use source and destination mac address for hashing ? 01 use source mac address for hashing ? 10 use destination mac address for hashing ? 11 use source destination mac address and ingress physical port number for hashing 7210 port select ZL50415 data sheet 42 zarlink semiconductor inc. 12.4.4 tx_age ? tx queue aging timer ?i 2 c address: h07;cpu address:h325 ? accessed by serial interface (rw) ? bit [5:0]: unit of 100 ms (default 8) ? disable transmission queue aging if value is zero. aging timer for all ports and queues. ? for no packet loss flow control, this register must be set to 0 12.5 group 4 address search engine group 12.5.1 agetime_low ? mac address aging time low ?i 2 c address h0a8; cpu address:h400 ? accessed by serial interface and i 2 c (r/w) ? bit [7:0] low byte of the mac address aging timer ? mac address aging is enable/disable by boot strap tstout9 12.5.2 agetime_high ?m ac address aging time high ?i 2 c address h0a9; cpu address h401 ? accessed by serial interface and i 2 c (r/w) ? bit [7:0]: high byte of the mac address aging timer ? the default setting provide 300 seconds aging time. aging time is based on the following equation: ? {agetime_time,agetime_low} x (# of mac address entries in the memory x 100 sec). number of mac entries = 32 k when 1 mb is used. number of mac entries = 64 k when 2 mb is used. 12.5.3 se_opmode ? search engine operation mode ? cpu address:h403 ? accessed by serial interface (r/w) ? {se_opmode} x(# of entries 100 u sec) bit [1:0]: ? port selection in unmanaged mode. input pin trunk1 enable/disable trunk group 1. ?00 reserved ? 01 port 4 and 5 are used for trunk1 ?10 reserved ? 11 port 4, 5, 6 and 7 are used for trunk1 765 0 tx queue agent 76 5 0 sl dms ZL50415 data sheet 43 zarlink semiconductor inc. 12.6 group 5 address buffer control/qos group 12.6.1 fcbat ? fcb aging timer ?i 2 c address h0aa; cpu address:h500 12.6.2 qosc ? qos control ?i 2 c address h0ab; cpu address:h501 ? accessed by serial interface and i 2 c (r/w) bit [5:0]: ? reserved bit [6]: ? disable mct speedup aging ? 1 ? disable speedup aging when mct resource is low ? 0 ? enable speedup aging when mct resource is low bit [7]: ? slow learning ? 1? enable slow learning. learning is temporary disabled when search demand is high ? 0 ? learning is performed independent of search demand 70 fcbat bit [7:0]: ? fcb aging time. unit of 1ms. ( default ff ) ? this function is for buffer aging control. it is used to configure the aging time, and can be enabled/ disabled through bootstrap pin. it is not recommended to use this function for normal operation. 76 5 43 10 tos-d tos-p vf1c l bit [0]: ? qos frame lost is ok. priority will be available fo r flow control enabled source only when this bit is set (default 0) bit [4]: ? per vlan multicast flow control (default 0) ? 0 ? disable ? 1 ? enable bit [5]: ? reserved ZL50415 data sheet 44 zarlink semiconductor inc. 12.6.3 fcr ? flooding control register ?i 2 c address h0ac; cpu address:h502 ? accessed by serial interface and i 2 c (r/w) bit [6]: ? select tos bits for priority (default 0) ? 0 - use tos [4:2] bits to map the transmit priority ? 1 - use tos [7:5] bits to map the transmit priority bit [7]: ? select tos bits for drop priority (default 0) ?0 - use tos [4:2] bits to map the drop priority ? 1 - use tos [7:5] bits to map the drop priority 76 43 0 tos timebase u2mr bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of fl ooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to di sable this function, program u2mr to 0. ( default = 8 ) bit [6:4]: ? timebase: 000 = 100 us 001 = 200 us 010 = 400 us 011 = 800 us 100 = 1.6 ms 101 = 3.2 ms 110 = 6.4 ms 111 = 100 us (same as 000) ? (default = 000) bit [7]: ? select vlan tag or tos (ip packets) to be preferentially picked to map transmit priority and drop priority ( default = 0 ). ? 0 ? select vlan tag priority field over tos ? 1 ? select tos over vlan tag priority field ZL50415 data sheet 45 zarlink semiconductor inc. 12.6.4 avpml ? vlan priority map ?i 2 c address h0ad; cpu address:h503 ? accessed by serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into ei ght internal level transmit priorities. under the internal transmit priority, seven is highest priority where as zero is the lowest. this feature allows the user the flexibility of redefini ng the vlan priority field. for example, programming a value of 7 into bit 2:0 of the avpml register would map vlan priority 0 into internal transmit priority 7. the new priority is used inside the ZL50415. when the packet goes out it carries the original priority. 12.6.5 avpmm ? vlan priority map ?i 2 c address h0ae, cpu address:h504 ? accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 12.6.6 avpmh ? vlan priority map ?i 2 c address h0af, cpu address:h505 ? accessed by serial interface and i 2 c (r/w) 76 5 32 0 vp2 vp1 vp0 bit [2:0]: ? priority when the vlan tag priority field is 0 (default 0) bit [5:3]: ? priority when the vlan tag priority field is 1 (default 0) bit [7:6]: ? priority when the vlan tag priority field is 2 (default 0) 7 6 43 10 vp5 vp4 vp3 vp2 bit [0]: ? priority when the vlan tag priority field is 2 (default 0) bit [3:1]: ? priority when the vlan tag priority field is 3 (default 0) bit [6:4]: ? priority when the vlan tag priority field is 4 (default 0) bit [7]: ? priority when the vlan tag priority field is 5 (default 0) 754210 vp7 vp6 vp5 ZL50415 data sheet 46 zarlink semiconductor inc. map vlan priority into eight level transmit priorities: 12.6.7 tospml ? tos priority map ?i 2 c address h0b0, cpu address:h506 ? accessed by serial interface and i 2 c (r/w) map tos field in ip packet into eight level transmit priorities 12.6.8 tospmm ? tos priority map ?i 2 c address h0b1, cpu address:h507 ? accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level tran smit priorities 12.6.9 tospmh ? tos priority map ?i 2 c address h0b2, cpu address:h508 ? accessed by serial interface and i 2 c (r/w) bit [1:0]: ? priority when the vlan tag priority field is 5 (default 0) bit [4:2]: ? priority when the vlan tag priority field is 6 (default 0) bit [7:5]: ? priority when the vlan tag priority field is 7 (default 0) 765 32 0 tp2 tp1 tp0 bit [2:0]: ? priority when the tos field is 0 (default 0) bit [5:3]: ? priority when the tos field is 1 (default 0) bit [7:6]: ? priority when the tos field is 2 (default 0) 76 43 10 tp5 tp4 tp3 tp2 bit [0]: ? priority when the tos field is 2 (default 0) bit [3:1]: ? priority when the tos field is 3 (default 0) bit [6:4]: ? priority when the tos field is 4 (default 0) bit [7]: ? priority when the tos field is 5 (default 0) 754 210 tp7 tp6 tp5 ZL50415 data sheet 47 zarlink semiconductor inc. map tos field in ip packet into four level transm it priorities: 12.6.10 avdm ? vlan discard map ?i 2 c address h0b3, cpu address:h509 ? accessed by serial interface and i 2 c (r/w) map vlan priority into frame discard when low priority buffer usage is above threshold 12.6.11 tosdml ? tos discard map ?i 2 c address h0b4, cpu address:h50a ? accessed by serial interface and i 2 c (r/w) map tos into frame discard when low priority buffer usage is above threshold bit [1:0]: ? priority when the tos field is 5 (default 0) bit [4:2]: ? priority when the tos field is 6 (default 0) bit [7:5]: ? priority when the tos field is 7 (default 0) 76543210 fdv7 fdv6 fdv5 fdv4 fdv3 fdv2 fdv2 fdv0 bit [0]: ? frame drop priority when vlan tag priority field is 0 (default 0) bit [1]: ? frame drop priority when vlan tag priority field is 1 (default 0) bit [2]: ? frame drop priority when vlan tag priority field is 2 (default 0) bit [3]: ? frame drop priority when vlan tag priority field is 3 (default 0) bit [4]: ? frame drop priority when vlan tag priority field is 4 (default 0) bit [5]: ? frame drop priority when vlan tag priority field is 5 (default 0) bit [6]: ? rame drop priority when vlan tag priority field is 6 (default 0) bit [7]: ? frame drop priority when vlan tag priority field is 7 (default 0) 7 6 543 2 10 fdt7 fdt6 fdt5 fdt4 fdt3 fdt2 fdt1 fdt0 bit [0]: ? frame drop priority when tos field is 0 (default 0) bit [1]: ? frame drop priority when tos field is 1 (default 0) bit [2]: ? frame drop priority when tos field is 2 (default 0) bit [3]: ? frame drop priority when tos field is 3 (default 0) bit [4]: ? frame drop priority when tos field is 4 (default 0) bit [5]: ? frame drop priority when tos field is 5 (default 0) bit [6]: ? frame drop priority when tos field is 6 (default 0) ZL50415 data sheet 48 zarlink semiconductor inc. 12.6.12 bmrc - broadcas t/multicast rate control ?i 2 c address h0b5, cpu address:h50b) ? accessed by serial interface and i 2 c (r/w) ? this broadcast and multicast rate def ines for each port the number of packet allowed to be forwarded within a specified time. once the packet rate is reached, packets will be dropped. to turn off the rate limit, program the field to 0. timebase is based on register 502 [6:4]. 12.6.13 ucc ? unicast congestion control ?i 2 c address h0b6, cpu address: 50c ? accessed by serial interface and i 2 c (r/w) 12.6.14 mcc ? multicast congestion control ?i 2 c address h0b7, cpu address: 50d ? accessed by serial interface and i 2 c (r/w) bit [7]: ? frame drop priority when tos field is 7 (default 0) 7430 broadcast rate multicast rate bit [3:0] : ? multicast rate control number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4] : ? broadcast rate control number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) 70 unicast congest threshold bit [7:0] : ? number of frame count. used for best effort dropping at b% when destination port?s best effort queue reaches ucc threshold and shared pool is all in use. granularity 1 frame. (default: h10 for 2 mb or h08 for 1mb) 754 0 fc reaction prd multicast congest threshold bit [4:0]: ? in multiples of two. used for triggering mc flow control when destination multicast port?s best ef fort queue reaches mcc threshold. (default 0x10) ZL50415 data sheet 49 zarlink semiconductor inc. 12.6.15 pr100 ? port reservation for 10/100 ports ?i 2 c address h0b8, cpu address 50e ? accessed by serial interface and i 2 c (r/w) 12.6.16 sfcb ? share fcb size ?i 2 c address h0ba), cpu address 510 ? accessed by serial interface and i 2 c (r/w) 12.6.17 c2rs ? class 2 reserve size ?i 2 c address h0bb, cpu address 511 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 2 (third lowest priority). granularity 1. (default 0) bit [7:5]: ? flow control reaction period (default 2) granularity 4 usec. 7430 buffer low thd sp buffer reservation bit [3:0]: ? per port buffer reservation. ? define the space in the fdb reserved for each 10/100 port. expressed in multiples of 4 packets. for each packet 1536 bytes are reserved in the memory. bits [7:4]: ? expressed in multiples of 4 packets. threshold for dropping all best effort frames when destination port best efforts queues reach ucc threshold and shared pool all used and source port reservation is at or below the pr100[7:4] level. also t he threshold for initiating uc flow control. ? default: - h58 for configuration with 2 mb; - h35 for configuration with 1 mb; 70 shared buffer size bits [7:0]: ? expressed in multiples of 4 packets. buffer reservation for shared pool. ? default: - he6 for configuration with memory of 2 mb; - h46 for configuration with memory of 1 mb; 70 class 2 fcb reservation ZL50415 data sheet 50 zarlink semiconductor inc. 12.6.18 c3rs ? class 3 reserve size ?i 2 c address h0bc, cpu address 512 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 3. granularity 1. (default 0) 12.6.19 c4rs ? class 4 reserve size ?i 2 c address h0bd, cpu address 513 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 4. granularity 1. (default 0) 12.6.20 c5rs ? class 5 reserve size ?i 2 c address h0be; cpu address 514 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 5. granularity 1. (default 0) 12.6.21 c6rs ? class 6 reserve size ?i 2 c address h0bf; cpu address 515 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 6 (secon d highest priority). granularity 1. (default 0) 12.6.22 c7rs ? class 7 reserve size ?i 2 c address h0c0; cpu address 516 ? accessed by serial interface and i 2 c (r/w) ? buffer reservation for class 7 (highest priority). granularity 1. (default 0) 70 class 3 fcb reservation 70 class 4 fcb reservation 70 class 5 fcb reservation 70 class 6 fcb reservation 70 class 7 fcb reservation ZL50415 data sheet 51 zarlink semiconductor inc. 12.6.23 classes byte limit set 0 ? accessed by serial interface and i 2 c (r/w): c ? qosc00 ? byte_c01 (i 2 c address h0c1, cpu address 517) b ? qosc01 ? byte_c02 (i 2 c address h0c2, cpu address 518) a ? qosc02 ? byte_c03 (i 2 c address h0c3, cpu address 519) qosc00 through qosc02 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme described in chapter 7.7. there are four such sets of valu es a-c specified in classes byte limit set 0, 1, 2 and 3. each 10/ 100 port can choose one of the four byte limit sets as specified by the qos select field located in bits 5 to 4 of the ecr2n register. the values a-c are per-q ueue byte thresholds for random early drop. qosc02 represents a, and qosc00 represents c. granularity when delay bound is used: qosc02: 128 byte s, qosc01: 256 bytes. qosc 00: 512 bytes. granularity when wfq is used: qosc02: 512 bytes, qosc01: 512 bytes, qosc00: 512 bytes. 12.6.24 classes byte limit set 1 ? accessed by serial interface and i 2 c (r/w): c - qosc03 ? byte_c11 (i 2 c address h0c4, cpu address 51a) b - qosc04 ? byte_c12 (i 2 c address h0c5, cpu address 51b) a - qosc05 ? byte_c13 (i 2 c address h0c6, cpu address 51c) qosc03 through qosc05 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc05: 128 byte s, qosc04: 256 bytes. qosc 03: 512 bytes. granularity when wfq is used: qosc05: 512 bytes, qosc04: 512 bytes, qosc03: 512 bytes. 12.6.25 classes byte limit set 2 ? accessed by serial interface and i 2 c (r/w): c - qosc06 ? byte_c21 (cpu address 51d) b - qosc07 ? byte_c22 (cpu address 51e) a - qosc08 ? byte_c23 (cpu address 51f) qosc06 through qosc08 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc08: 128 byte s, qosc07: 256 bytes. qosc 06: 512 bytes. granularity when wfq is used: qosc08: 512 bytes, qosc07: 512 bytes, qosc06: 512 bytes. ZL50415 data sheet 52 zarlink semiconductor inc. 12.6.26 classes byte limit set 3 ? accessed by serial interface and i 2 c (r/w): c - qosc09 ? byte_c31 (cpu address 520) b - qosc10 ? byte_c32 (cpu address 521) a - qosc11 ? byte_c33 (cpu address 522) qosc09 through qosc011 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc11: 128 byte s, qosc10: 256 bytes. qosc09: 512 bytes. granularity when wfq is used: qosc11: 512 bytes, qosc10: 512 bytes, qosc09: 512 bytes. 12.6.27 classes wfq credit set 0 ? accessed by serial interface (r/w) w0 - qosc24[5:0] ? credit_c00 (cpu address 52f) w1 - qosc25[5:0] ? credit_c01 (cpu address 530) w2 - qosc26[5:0] ? credit_c02 (cpu address 531) w3 - qosc27[5:0] ? credit_c03 (cpu address 532) qosc24 through qosc27 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the number s is 1 and their sum must be 64. qosc27 corresponds to w3 and qosc24 corresponds to w0. ? qosc24[7:6]: priority service type for the ports select this parameter set. option 1 to 4. ? qosc25[7]: priority service allow flow control for the ports select this parameter set. ? qosc25[6]: flow control pause best effort traffic only both flow control allow and flow control best effort only can take effect only the priority type is wfq. 12.6.28 classes wfq credit set 1 ? accessed by serial interface (r/w) w0 - qosc28[5:0] ? credit_c10 (cpu address 533) w1 - qosc29[5:0] ? credit_c11 (cpu address 534) w2 - qosc30[5:0] ? credit_c12 (cpu address 535) w3 - qosc31[5:0] ? credit_c13 (cpu address 536) qosc28 through qosc31 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the number s is 1 and their sum must be 64. qosc31 corresponds to w3 and qosc28 corresponds to w0. ? qosc28[7:6]: priority service type for the ports select this parameter set. option 1 to 4. ? qosc29[7]: priority service allow flow cont rol for the ports select this parameter set. ? qosc29[6]: flow control pause best effort traffic only ZL50415 data sheet 53 zarlink semiconductor inc. 12.6.29 classes wfq credit set 2 ? accessed by serial interface (r/w) w0 - qosc32[5:0] ? credit_c20 (cpu address 537) w1 - qosc33[5:0] ? credit_c21 (cpu address 538) w2 - qosc34[5:0] ? credit_c22 (cpu address 539) w3 - qosc35[5:0] ? credit_c23 (cpu address 53a) qosc35 through qosc32 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the number s is 1 and their sum must be 64. qosc35 corresponds to w3 and qosc32 corresponds to w0. ? qosc32[7:6]: priority service type for the ports select this parameter set. option 1 to option 4. ? qosc33[7]: priority service allow flow cont rol for the ports select this parameter set. ? qosc33[6]: flow control pause best effort traffic only 12.6.30 classes wfq credit set 3 ? accessed by serial interface (r/w) w0 - qosc36[5;0] ? credit_c30 (cpu address 53b) w1 - qosc37[5:0] ? credit_c31 (cpu address 53c) w2 - qosc38[5:0] ? credit_c32 (cpu address 53d) w3 - qosc39[5:0] ? credit_c33 (cpu address 53e) qosc39 through qosc36 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the number s is 1 and their sum must be 64. qosc39 corresponds to w3 and qosc36 corresponds to w0. ? qosc36[7:6]: priority service type for the ports select this parameter set. option 1 to option 4. ? qosc37[7]: priority service allow flow cont rol for the ports select this parameter set. ? qosc37[6]: flow control pause best effort traffic only 12.6.31 rdrc0 ? wred rate control 0 ?i 2 c address 0fb, cpu address 553 ? accessed by serial interface and i c c (r/w) 7430 x rate y rate bits [7:4]: ? corresponds to the frame drop percentage x% for wred. granularity 6.25%. bits [3:0]: ? corresponds to the frame drop percentage y% for wred. granularity 6.25%. see programming qos registers applic ation note for more information. ZL50415 data sheet 54 zarlink semiconductor inc. 12.6.32 rdrc1 ? wred rate control 1 ?i 2 c address 0fc, cpu address 554 ? accessed by serial interface and i 2 c (r/w) 12.6.33 user defined logical ports and well known ports the ZL50415 supports classifying packet priority through laye r 4 logical port information. it can be setup by 8 well known ports, 8 user defined logical ports, and 1 user defined range. the 8 well known ports supported are: ?0:23 ? 1:512 ? 2:6000 ? 3:443 ? 4:111 ? 5:22555 ?6:22 ? 7:554 their respective priority can be programmed via well_known_port [7:0] priority register. well_known_port_ enable can individually turn on/off each well known port if desired. similarly, the user defined logical port provides the user program mability to the priority, pl us the flexibility to select specific logical ports to fit the app lications. the 8 user logical ports can be programmed via user_port 0-7 registers. two registers are required to be programmed for the logical port number. the respective priority can be programmed to the user_port [7:0] priority register. the port priority can be individually enabled/disabled via user_port_enable register. the user defined range provides a range of logical port numbers with the same priori ty level. programming is similar to the user defined logical port. instead of progr amming a fixed port number, an upper and lower limit need to be programmed, they are: {rhighh, rhighl} and {r lowh, rlowl} respectively. if the value in the upper limit is smaller or equal to the lower limi t, the function is disabled. any ip pack et with a logical port that is less than the upper limit and more than the lower limit will use the priori ty specified in rpriority. 7430 z rate b rate bits [7:4]: ? corresponds to the frame drop percentage z% for wred. granularity 6.25%. bits [3:0]: ? corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. granularity 6.25%. see programming qos register application note for more information. ZL50415 data sheet 55 zarlink semiconductor inc. 12.6.33.1 user_port0_(0~7) ? user define logical port (0~7) ? user_port_0 - i 2 c address h0d6 + 0de; cpu address 580(low) + 581(high) ? user_port_1 - i 2 c address h0d7 + 0df; cpu address 582 + 583 ? user_port_2 - i 2 c address h0d8 + 0e0; cpu address 584 + 585 ? user_port_3 - i 2 c address h0d9 + 0e1; cpu address 586 + 587 ? user_port_4 - i 2 c address h0da + 0e2; cpu address 588 + 589 ? user_port_5 - i 2 c address h0db + 0e3; cpu address 58a + 58b ? user_port_6 - i 2 c address h0dc + 0e4; cpu address 58c + 58d ? user_port_7 - i 2 c address h0dd + 0e5; cpu address 58e + 58f ? accessed by serial interface and i 2 c (r/w) ? (default 00) this register is duplicated eight times from port 0 through port 7 and allows the definition of eight separate ports 12.6.33.2 user_port_[1:0]_priority - user define logic port 1 and 0 priority ?i 2 c address h0e6, cpu address 590 ? accessed by serial interface and i 2 c (r/w) ? the chip allows the defi nition of the priority 12.6.33.3 user_port_[3:2]_priority - user define logic port 3 and 2 priority ?i 2 c address h0e7, cpu address 591 ? accessed by serial interface and i 2 c (r/w) 70 tcp/udp logic port low 70 tcp/udp logic port high 7543 10 priority 1 drop priority 0 drop bits [3:0]: ? priority setting, transmi ssion + dropping, for logic port 0 bits [7:4]: ? priority setting, transmission + dropping, for logic port 1 (default 00) 754310 priority 3 drop priority 2 drop ZL50415 data sheet 56 zarlink semiconductor inc. 12.6.34 user_port_[5:4]_priority - user define logic port 5 and 4 priority ?i 2 c address h0e8, cpu address 592 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.35 user_port_[7:6]_priority - user define logic port 7 and 6 priority ?i 2 c address h0e9, cpu address 593 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.36 user_port_enable [7:0] ? us er define logic 7 to 0 port enables ?i 2 c address h0ea, cpu address 594 ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.36.1 well_known_port [1:0] priority- well known logic port 1 and 0 priority ?i 2 c address h0eb, cpu address 595 ? accessed by serial interface and i 2 c (r/w) ? priority 0 - well known port 23 for telnet applications. ? priority 1 - well known port 512 for tcp/udp ? (default 00) 12.6.36.2 well_known_port [3:2] priority- well known logic port 3 and 2 priority ?i 2 c address h0ec, cpu address 596 ? accessed by serial interface and i 2 c (r/w) ? priority 2 - well known port 6000 for xwin. ? priority 3 - well known port 443 for http. sec ? (default 00) 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 754310 priority 1 drop priority 0 drop 754310 priority 3 drop priority 2 drop ZL50415 data sheet 57 zarlink semiconductor inc. 12.6.36.3 well_known_port [5:4] priority- well known logic port 5 and 4 priority ?i 2 c address h0ed, cpu address 597 ? accessed by serial interface and i 2 c (r/w) ? priority 4 - well known port 111 for sun rpe. ? priority 5 - well known port 22555 for ip phone call setup. ? (default 00) 12.6.36.4 well_known_port [7:6] priority- well known logic port 7 and 6 priority ?i 2 c address h0ee, cpu address 598 ? accessed by serial interface and i 2 c (r/w) ? priority 6 - well known port 22 for ssh. ? priority 7 - well known port 554 for rtsp. ? (default 00) 12.6.36.5 well known_port_enable [7:0] ? well known logic 7 to 0 port enables ?i 2 c address h0ef, cpu address 599 ? accessed by serial interface and i 2 c (r/w) ?1 - enable ? 0 - disable ? (default 00) rlowl ? user define range low bit 7:0 ?i 2 c address h0f4, cpu address: 59a ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.36.6 rlowh ? user define range low bit 15:8 ?i 2 c address h0f5, cpu address: 59b ? accessed by serial interface and i 2 c (r/w) ? (default 00) 75 4 3 1 0 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 ZL50415 data sheet 58 zarlink semiconductor inc. 12.6.36.7 rhighl ? user define range high bit 7:0 ?i 2 c address h0d3, cpu address: 59c ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.36.8 rhighh ? user define range high bit 15:8 ?i 2 c address h0d4, cpu address: 59d ? accessed by serial interface and i 2 c (r/w) ? (default 00) 12.6.36.9 rpriority ? user define range priority ?i 2 c address h0d5, cpu address: 59e ? accessed by serial interface and i 2 c (r/w) ? rlow and rhigh form a range for logical ports to be classified with priority specified in rpriority. 12.7 group 6 address misc group 12.7.1 mii_op0 ? mii register option 0 ?i 2 c address f0, cpu address:h600 ? accessed by serial interface and i 2 c (r/w) 743 10 range transmit priority drop bit [3:1] ? transmit priority bits [0]: ? drop priority 76 5 4 0 hfc 1prst disj vendor spc. reg addr bits [7]: ? half duplex flow control feature ? 0 = half duplex flow control always enable ? 1 = half duplex flow control by negotiation bits [6]: ? link partner reset auto-negotiate disable bits [5]: ? disable jabber detection. this is for homepna application or any serial operation slower than 10 mbps. ? 1 = disable ? 0 = enable bit [4:0]: ? vendor specified link status register address (null value means don?t use it) (default 00); used when the linkup bit position in the phy is non-standard. ZL50415 data sheet 59 zarlink semiconductor inc. 12.7.2 mii_op1 ? mii register option 1 ?i 2 c address f1, cpu address:h601 ? accessed by serial interface and i 2 c (r/w) 12.7.3 fen ? feature register ?i 2 c address f2, cpu address:h602 ? accessed by serial interface and i 2 c (r/w) 12.7.4 miic0 ? mii command register 0 ? cpu address:h603 ? accessed by serial interface only (r/w) ? bit [7:0] mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 743 0 speed bit location duplex bit location bits [3:0]: ? duplex bit location in vendor specified register bits [7:4]: ? speed bit location in vendor specified register (default 00) 765 3210 dml mii ds bits [1:0]: ? reserved (default 0) bit [2]: ? support ds ef code. (default 0) ? when 101110 is detected in ds field (tos [7:2]), the frame priority is set for 110 and drop is set for 0. bit [5:3]: ? reserved (default 010) bit [6]: ? disable mii management state machine ? 0: enable mii management state machine (default 0) ? 1: disable mii management state machine bit [7]: ? disable using mct link list structure ? 0: enable using mct link list structure (default 0) ? 1: disable using mct link list structure ZL50415 data sheet 60 zarlink semiconductor inc. 12.7.5 miic1 ? mii command register 1 ? cpu address:h604 ? accessed by serial interface only (r/w) ? bit [7:0] mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 12.7.6 miic2 ? mii command register 2 ? cpu address:h605 ? accessed by serial interface only (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. writing to th is register will initiate a serial m anagement cycle to the mii management interface. for detail information, please refer to the phy control application note. 12.7.7 mic3 ? mii command register 3 ? cpu address:h606 ? accessed by serial interface only (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 12.7.8 miid0 ? mii data register 0 ? cpu address:h607 ? accessed by serial interface only (ro) ? bit [7:0] mii data [7:0] 76 54 0 mii op register address bits [4:0]: ? reg_ad ? register phy address bit [6:5] ? op ? operation code ?10? for read command and ?01? for write command 7654 0 rdy valid phy address bits [4:0]: ? phy_ad ? 5 bit phy address bit [6] ? valid ? data valid from phy (read only) bit [7] ? rdy ? data is returned from phy (ready only) ZL50415 data sheet 61 zarlink semiconductor inc. 12.7.9 miid1 ? mii data register 1 ? cpu address:h608 ? accessed by serial interface only (ro) ? bit [7:0] mii data [15:8] 12.7.10 led mode ? led control ? cpu address:h609 ? accessed by serial interface and i 2 c (r/w) 12.7.11 checksum - eeprom checksum ?i 2 c address ff, cpu address:h60b ? accessed by serial interface and i 2 c (r/w) before requesting that th e ZL50415 updates the eeprom device , the correct checksum needs to be calculated and written into this chec ksum register. when the zl 50415 boots from the eeprom the checksum is calculated and the value must be zero. if the checksum is not ze roed the ZL50415 does not start and pin checksum_ok is set to zero. the checksum formula is: ff i 2 c register = 0 i=0 7543210 clock rate hold time bit [0] ? reserved (default 0) bit [2:1]: ? hold time for led signal (default= 00) 00 = 8 msec 01 = 16 msec 10 = 32 msec 11 = 64 msec bit [4:3]: ? led clock frequency (default 0) 00 = 100 m/8 =12.5 mhz 01 = 100 m/16 = 25 mhz 10 = 100 m/32= 125 mhz 11 = 100 m/64 = 1.5625 mhz bit [7:5]: ? reserved. must be 0. (default 0) bit [7:0]: ? (default 0) ZL50415 data sheet 62 zarlink semiconductor inc. 12.8 group 7 address port mirroring group 12.8.1 mirror1_src ? port mirror source port ? cpu address 700 ? accessed by serial interface (r/w) (default 7f) 12.8.2 mirror1_dest ? port mirror destination ? cpu address 701 ? accessed by serial interface (r/w) (default 17) 12.8.3 mirror2_src ? port mirror source port ? cpu address 702 ? accessed by serial interface (r/w) (default ff) 7654 0 ov i/o src port select bit [4:0]: ? source port to be mirrored. use illegal port number to disable mirroring bit [5]: ? 1 ? select ingress data ? 0 ? select egress data bit [7]: ? must be ?1? 754 0 dest port select bit [4:0]: ? port mirror destination 7654 0 i/o src port select bit [4:0]: ? source port to be mirrored. use illegal port number to disable mirroring bit [5]: ? 1 ? select ingress data ? 0 ? select egress data bit [7] ? must be 1 ZL50415 data sheet 63 zarlink semiconductor inc. 12.8.4 mirror2_dest ? port mirror destination ? cpu address 703 ? accessed by serial interface (r/w) (default 00) 12.9 group f address cpu access group 12.9.1 gcr-global control register ? cpu address: hf00 ? accessed by serial interface. (r/w) 12.9.2 dcr-device stat us and signature register ? cpu address: hf01 ? accessed by serial interface. (ro) 754 0 dest port select bit [4:0]: ? port mirror destination 743210 reset bist sr sc bit [0]: ? store configuration (default = 0) ? write ?1? followed by ?0? to stor e configuration into external eeprom bit [1]: ? store configuration and reset (default = 0) ? write ?1? to store configuration into external eeprom and reset chip bit [2]: ? start bist (default = 0) ? write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit [3]: ? soft reset (default = 0) ? write ?1? to reset chip bit [4]: ? reserved 765 43210 revision signature re binp br bw bit [0]: ? 1: busy writing configuration to i 2 c ? 0: not busy writing configuration to i 2 c ZL50415 data sheet 64 zarlink semiconductor inc. 12.9.3 dcr1-chip status ? cpu address: hf02 ? accessed by serial interface (ro) bit [1]: ? 1: busy reading configuration from i 2 c ? 0: not busy reading configuration from i 2 c bit [2]: ? 1: bist in progress ? 0: bist not running bit [3]: ? 1: ram error ? 0: ram ok bit [5:4]: ? device signature ? 01: ZL50415 device bit [7:6]: ? revision ? 00: initial silicon ? 01: xa1 silicon ? 10: production silicon 76 0 cic bit [7] ? chip initialization completed ZL50415 data sheet 65 zarlink semiconductor inc. 12.9.4 dpst ? device port status register ? cpu address:hf03 ? accessed by serial interface (r/w) bit [4:0]: ? read back index register. this is used for selecting what to read back from dtst. (default 00) - 5?b00000 ? port 0 operating mode and negotiation status - 5?b00001 ? port 1 operating mode/neg status - 5?b00010 ? port 2 operating mode/neg status - 5?b00011 ? port 3 operating mode/neg status - 5?b00100 ? port 4 operating mode/neg status - 5?b00101 ? port 5 operating mode/neg status - 5?b00110 ? port 6 operating mode/neg status - 5?b00111 ? port 7 operating mode/neg status - 5?b01000 ? port 8 operating mode/neg status - 5?b01001 ? port 9 operating mode/neg status - 5?b01010 ? port 10 operating mode/neg status - 5?b01011 ? port 11 operating mode/neg status - 5?b01100 ? port 12 operating mode/neg status - 5?b01101 ? port 13 operating mode/neg status - 5?b01110 ? port 14 operating mode/neg status - 5?b01111 ? port 15 operating mode/neg status - 5?b10xxx ? reserved ZL50415 data sheet 66 zarlink semiconductor inc. 12.9.5 dtst ? data read back register ? cpu address: hf04 ? accessed by serial interface (ro) ? this register provides various internal information as selected in dpst bit [4:0]. refer to the phy control application note. when bit is 1: ? bit [0] ? flow control enable ? bit [1] ? full duplex port ? bit [2] ? fast ethernet port ? bit [3] ? link is down ? bit [7:4] ? reserved 12.9.6 pllcr - pll control register ? cpu address: hf05 ? accessed by serial interface (rw) bit [3]must be '1' bit [7]selects strap option or lclk/oeclk registers 0 - strap option (default) 1 - lclk/oeclk registers 12.9.6.1 lclk - la_clk delay from internal oe_clk ? cpu address: hf06 ? accessed by serial interface (rw) pd[12:10] lclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay 010b 20h 6 buffers delay 011b 10h 5 buffers delay (recommend) 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay the lclk delay from sclk is the sum of the delay programmed in here and the delay in oeclk register. 7 43210 inkdn fe fdpx fcen ZL50415 data sheet 67 zarlink semiconductor inc. 12.9.7 oeclk - internal oe_clk delay from sclk ? cpu address: hf07 ? accessed by serial interface (rw) the oe_clk is used for generating the oe0 and oe1 signals. pd[15:13] oeclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay (recommend) 010b 20h 6 buffers delay 011b 10h 5 buffers delay 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay 12.9.8 da ? da register ? cpu address: hfff ? accessed by serial interface (ro) ? always return 8?h da . indicate the serial port connection is good. ZL50415 data sheet 68 zarlink semiconductor inc. 13.0 bga and ba ll signal descriptions 13.1 bga views (top - view) 13.1.1 encapsulated view a la_d 4 la_d 7 la_d 10 la_d 13 la_d 15 la_a 4 la_o e0_ la_a 8 la_a 13 la_a 16 la_a 19 la_d 33 la_d 36 la_d 39 la_d 42 la_d 45 oe_ clk0 la_ clk0 tru nk1 rese rved rese rved scl sda stro be tsto ut7 b la_d 1 la_d 3 la_d 6 la_d 9 la_d 12 la_d 14 la_a dsc_ la_o e1_ la_a 7 la_a 12 la_a 15 la_a 18 la_d 32 la_d 35 la_d 38 la_d 41 la_d 44 oe_ clk1 la_ clk1 la_d 62 rese rved rese rved rese rved rese rved d0 tsto ut8 tsto ut3 c la_c lk la_d 0 la_d 2 la_d 5 la_d 8 la_d 11 la_a 3 la_o e_ la_w e_ t_mo de1 la_a 11 la_a 14 la_a 17 la_a 20 la_d 34 la_d 37 la_d 40 la_d 43 oe_ clk2 la_ clk2 p_d trun k0 rese rved rese rved auto fd tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agn d la_d 17 la_d 19 la_d 21 la_d 23 la_d 25 la_d 27 la_d 29 la_d 31 la_a 6 la_a 10 la_w e0_ la_d 49 la_d 51 la_d 53 la_d 55 la_d 57 la_d 59 la_d 61 la_d 63 la_d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 e sclk la_d 16 la_d 18 la_d 20 la_d 22 la_d 24 la_d 26 la_d 28 la_d 30 la_a 5 la_a 9 la_w e1_ la_d 48 la_d 50 la_d 52 la_d 54 la_d 56 la_d 58 la_d 60 rese rved la_d 46 scan link tsto ut15 rese rved rese rved scan mod e tsto ut6 tsto ut2 f avc c resi n_ scan en rese rved rese rved vcc vcc vcc vcc vcc rese rved rese rved rese rved rese rved rese rved g rese rved rese tout _ rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved h rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved j rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved k rese rved rese rved rese rved rese rved rese rved vdd vdd vdd vdd rese rved rese rved rese rved rese rved rese rved l rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved m rese rved rese rved rese rved rese rved rese rved vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved n rese rved rese rved rese rved rese rved rese rve d vcc vdd vss vss vss vss vss vss vss vdd vcc rese rve d rese rved rese rved p rese rved rese rved rese rved rese rved rese rve d vcc vss vss vss vss vss vss vss vcc rese rve d rese rved mdio rese rved r rese rved rese rved rese rved rese rved rese rve d vcc vss vss vss vss vss vss vss vcc rese rve d rese rved mdc m_cl k t rese rved rese rved rese rved rese rved rese rve d vcc vss vss vss vss vss vss vss vcc rese rve d rese rved rese rved rese rved rese rved u rese rved rese rved t_mo de0 rese rved rese rve d vcc vdd vss vss vss vss vss vss vss vdd vcc rese rve d rese rved rese rved rese rved rese rved v rese rved rese rved rese rved rese rved rese rved vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved w rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved y rese rved rese rved rese rved rese rved rese rved vdd vdd vdd vdd rese rved rese rved rese rved rese rved rese rved a a rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a b rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a c rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a d rese rved rese rved rese rved rese rved rese rved vcc vcc vcc vcc vcc rese rved rese rved rese rved rese rved rese rved a e m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3_r xd0 m5_t xd1 m5_t xen m5_r xd0 m8_t xd1 m8_t xen m8_r xd0 m10_ txd1 m10_ txen m10_ rxd0 m13_ txd1 rese rved m15_ txd1 rese rved m15_ txen m15_ rxd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved a f m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3_r xd1 m5_t xd0 m5_c rs m5_r xd1 m8_t xd0 m8_c rs m8_r xd1 m10_ txd0 m10_ crs m10_ rxd1 m13_ txd0 m13_ crs m13_ rxd1 m14_ crs rese rved m15_ rxd1 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a g m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4_t xd1 m4_c rs m6_t xd1 m6_c rs m7_t xd1 m7_c rs m9_t xd1 m9_c rs m11_ txd1 m11_ crs m12_ txd1 m12_ crs m14_ txd1 m15_ txd0 rese rved rese rve d rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved a h m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4_t xd0 m4_r xd0 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m9_t xd0 m9_r xd0 m11_ txd0 m11_ rxd0 m12_ txd0 m12_ rxd0 m14_ txd0 m14_ rxd0 m13_ rxd0 m15_ crs rese rved rese rved rese rved rese rved rese rved rese rved rese rved aj m1_r xd1 m2_t xen m2_r xd1 m4_t xen m4_r xd1 m6_t xen m6_r xd1 m7_t xen m7_r xd1 m9_t xen m9_r xd1 m11_ txen m11_ rxd1 m12_ txen m12_ rxd1 m14_ txen m14_ rxd1 rese rved m13_ txen rese rved rese rved rese rved rese rved rese rved rese rved 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ZL50415 data sheet 69 zarlink semiconductor inc. 13.2 ball ? signal descriptions all pins are cmos type; all input pins are 5 volt to lerance; and all output pins are 3.3 cmos drive. 13.2.1 ball signal descriptions ball no(s) symbol i/o description i 2 c interface note: use i 2 c and serial control interface to configure the system a24 scl output i 2 c data clock a25 sda i/o-ts with pull up i 2 c data i/o serial control interface a26 strobe input with weak internal pull up serial strobe pin b26 d0 input serial data input c25 autofd output with pull up serial data output (autofd) frame buffer interface d20, b21, d19, e19,d18, e18, d17, e17, d16, e16, d15, e15, d14, e14, d13, e13, d21, e21, a18, b18, c18, a17, b17, c17, a16, b16, c16, a15, b15, c15, a14, b14, d9, e9, d8, e8, d7, e7, d6, e6, d5, e5, d4, e4, d3, e3, d2, e2, a7, b7, a6, b6, c6, a5, b5, c5, a4, b4, c4, a3, b3, c3, b2, c2 la_d[63:0] i/o-ts with pull up frame bank a? data bit [63:0] c14, a13, b13, c13, a12, b12, c12, a11, b11, c11, d11, e11, a10, b10, d10, e10, a8, c7 la_a[20:3] output frame bank a ? address bit [20:3] b8 la_adsc# output with pull up frame bank a address status control c1 la_clk output frame bank a clock input c9 la_we# output with pull up frame bank a write chip select for one layer sram application d12 la_we0# output with pull up frame bank a write chip select for lowe r layer of two layers sram application e12 la_we1# output with pull up frame bank a write chip select for upper layer of two layers sram application c8 la_oe# output with pull up frame bank a read chip select for one layer sram application ZL50415 data sheet 70 zarlink semiconductor inc. a9 la_oe0# output with pull up frame bank a read chip select for lower layer of two layers sram application b9 la_oe1# output with pull up frame bank a read chip select for upper layer of two layers sram application fast ethernet access ports [15:0] rmii r28 m_mdc output mii management data clock ? (common for all mii ports [15:0]) p28 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ? [15:0])) r29 m_clki input reference input clock af21, aj19, af18, aj17, aj15, af15, aj13, af12, aj11, aj9, af9, aj7, af6, aj5, aj3, af1 m[15:0]_rxd[1] input with weak internal pull up resistors. ports [15:0] ? receive data bit [1] ae21, ah19, ah20, ah17, ah15, ae15, ah13, ae12, ah11, ah9, ae9, ah7, ae6, ah5, ah2, af2 m[15:0]_rxd[0] input with weak internal pull up resistors ports [15:0] ? receive data bit [0] ah21, af19, af17, ag17, ag15, af14, ag13, af11, ag11, ag9, af8, ag7, af5, ag5, ah3, af3 m[15:0]_crs_dv input with weak internal pull down resistors. ports [15:0] ? carrier sense and receive data valid ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[15:0]_txen i/o- ts with pull up, slew ports [15:0] ? transmit enable strap option for rmii/gpsi ae18, ag18, ae16, ag16, ag14, ae13, ag12, ae10, ag10, ag8, ae7, ag6, ae4, ag4, ag3, ae3 m[15:0]_txd[1] output, slew ports [15:0] ? transmit data bit [1] ag19, ah18, af16, ah16, ah14, af13, ah12, af10, ah10, ah8, af7, ah6, af4, ah4, ag2, ae2 m[15:0]_txd[0] output, slew ports [15:0] ? transmit data bit [0] led interface c29 led_clk/tstout0 i/o- ts with pull up led serial interface output clock d29 led_syn/tstout1 i/o- ts with pull up led output data stream envelope e29 led_bit/tstout2 i/o- ts with pull up led serial data output stream ball no(s) symbol i/o description ZL50415 data sheet 71 zarlink semiconductor inc. c27 init_done/tstout9 i/o- ts wit h pull up system start operation d27 init_start/tstout1 0 i/o- ts with pull up start initialization c26 checksum_ok/tsto ut11 i/o- ts with pull up eeprom read ok d26 fcb_err/tstout12 i/o- ts with pull up fcb memory self test fail d25 mct_err/tstout13 i/o- ts with pu ll up mct memory self test fail d24 bist_in_prc/tstout 14 i/o- ts with pull up processing memory self test e24 bist_done/tstout1 5 i/o- ts with pull up memory self test done trunk enable c22 trunk0 input w/ weak internal pull down resistors trunk port enable a21 trunk1 input w/ weak internal pull down resistors trunk port enable test facility u3 t_mode0 i/o-ts test pin ? set mode upon reset, and provides nand tree test output during test mode (pull up) c10 t_mode1 i/o-ts test pin ? set mode upon reset, and provides nand tree test output during test mode (pull up) t_mode1 t_mode0 0 0 nandtree 0 1 reserved 1 0 reserved 1 1 regular operation t_mode0 and t_mode1 are used for manufacturing tests. the signals should both be set to 1 for regular operation. f3 scan_en input with pull down scan enable 0 - normal mode (unconnected) e27 scanmode input with pull down 1 - enables test mode. 0 - normal mode (unconnected) ball no(s) symbol i/o description ZL50415 data sheet 72 zarlink semiconductor inc. system clock, power, and ground pins e1 sclk input system clock at 100 mhz k12, k13, k17,k18 m10, n10, m20, n20, u10, v10, u20, v20, y12, y13, y17, y18 vdd power +2.5 volt dc supply f13, f14, f15, f16, f17, n6, p6, r6, t6, u6, n24, p24, r24, t24, u24, ad13, ad14, ad15, ad16, ad17 vcc power +3.3 volt dc supply m12, m13, m14, m15, m16, m17, m18, n12, n13, n14, n15, n16, n17, n18, p12, p13, p14, p15, p16, p17, p18, r12, r13, r14, r15, r16, r17, r18, t12, t13, t14, t15, t16, t17, t18, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v18, vss power ground ground f1 avcc analog power analog +2.5 volt dc supply d1 agnd analog ground analog ground misc. d22 scancol input scans the collision signal of home phy d23 scanclk input/ output clock for scanning home phy collision and link e23 scanlink input link up signal from home phy f2 resin# input reset input g2 resetout# output reset phy ball no(s) symbol i/o description ZL50415 data sheet 73 zarlink semiconductor inc. b22, a22, c23, b23, a23, c24, f4, f5, g4, g5, h4, h5, j4, j5, k4, k5, l4, l5, m4, m5, n4, n5, g3, h1, h2, h3, j1, j2, j3, k1, k2, k3, l1, l2, l3, m1, m2, m3, u4, u5, v4, v5, w4, w5, y4, y5, aa4, aa5, ab4, ab5, ac4, ac5, ad4, ad5, w1, y1, y2, y3, aa1, aa2, aa3, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad3, n3, n2, n1, p3, p2, p1, r5, r4, r3, r2, r1, t5, t4, t3, t2, t1, w3, w2, v1, g1, v3, p4, p5, v2, u1, u2, u26, u25, v26, v25, w26, w25, y27, y26, aa26, aa25, ab26, ab25, ac26, ac25, ad26, ad25, t28, u28, r25, u29, t29, u27, v29, v28, v27, w29, w28, w27, y29, y28, y25, aa29, aa28, aa27, ab29, ab28, ab27, t26, r26, t27, t25, p29, g26, g25, h26, h25, j26, j25, k25, k26, m25, l26, m26, l25, n26, n25, p26, p25, f28, g28, e25, g29, f29, g27,h29, h28, h27, j29, j28, j27, k29, k28, k27, l29, l28, l27, m29, m28, m27, f26, e26, f27, f25, n29,b24, ac29, ae28, aj27, af27,aj25,af24,ah23, ae19,ac28, af28, ah27, ae27, ah25, ae24, af22, af20, ac27, af29, ag27, af26, ag25, ag23, af23, ag21, ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ad27, ah28, ag26, ae25, ag24, ae22, aj23, ag20, ad28, ag29, ah26, af25, ah24, ag22, ah22, ae17, e20, b25 reserved i/o-ts reserved pin bootstrap pins (default= pull up, 1= pull up 0= pull down) after reset tstout0 to tstout15 are used by the led interface. c29 tstout0 reserved ball no(s) symbol i/o description ZL50415 data sheet 74 zarlink semiconductor inc. d29 tstout1 default: enable (1) rmii mac power saving enable 0 - no power saving 1 - power saving c28, b28, e29 tstout[4:2] reserved d28 tstout5 default: sclk (1) scan speed 0 - o sclk(hpna) 1 - sclk e28 tstout6 reserved a27 tstout7 default: 128 k x 32 or 128 k x 64 (1) memory size 0 - 256 k x 32 or 256 k x 64 (4 m total) 1 - 128 k x 32 or 128 k x 64 (2 m total) b27 tstout8 default: not installed (1) eeprom installed 0 - eeprom installed 1 - eeprom not installed c27 tstout9 default: mct aging enable (1) mct aging 0 - mct aging disable 1 - mct aging enable d27 tstout10 default: fcb aging enable (1) fcb aging 0 - fcb aging disable 1 - fcb aging enable c26 tstout11 default: timeout reset enable (1) timeout reset 0 - time out reset disable 1 - time out reset enable. issue reset if any state machine did not go back to idle for 5 sec. d26 tstout12 reserved d25 tstout13 default: single depth (1) fdb ram depth (1 or 2 layers) 0 - two layers 1 - one layer d24 tstout14 reserved. e24 tstout15 default: normal operation sram test mode 0 - enable test mode 1 - normal operation ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1, m[15:0]_txen default: rmii 0 ? gpsi 1 - rmii c21 p_d must be pulled- down reserved - must be pulled- down ball no(s) symbol i/o description ZL50415 data sheet 75 zarlink semiconductor inc. note: 13.3 ball ? signal name c19, b19, a19 oe_clk[2:0] default: 111 programmable delay for internal oe_clk from sclk input. the oe_clk is used for generating the oe0 and oe1 signals suggested value is 001. c20, b20, a20 la_clk[2:0] default: 111 programmable delay for la_clk from internal oe_clk. the la_clk delay from sclk is the sum of the delay programmed in here and the delay in p_d[15:13]. suggested value is 011. # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output si gnal with open-drain driver ball no. signal name ball no. signal name ball no. signal name d20 la_d[63] d3 la_d[19] a9 la_oe0# b21 la_d[62] e3 la_d[18] b9 la_oe1# d19 la_d[61] d2 la_d[17] f4 reserved e19 la_d[60] e2 la_d[16] f5 reserved d18 la_d[59] a7 la_d[15] g4 reserved e18 la_d[58] b7 la_d[14] g5 reserved d17 la_d[57] a6 la_d[13] h4 reserved e17 la_d[56] b6 la_d[12] h5 reserved d16 la_d[55] c6 la_d[11] j4 reserved e16 la_d[54] a5 la_d[10] j5 reserved d15 la_d[53] b5 la_d[9] k4 reserved e15 la_d[52] c5 la_d[8] k5 reserved d14 la_d[51] a4 la_d[7] l4 reserved e14 la_d[50] b4 la_d[6] l5 reserved ball no(s) symbol i/o description ZL50415 data sheet 76 zarlink semiconductor inc. d13 la_d[49] c4 la_d[5] m4 reserved e13 la_d[48] a3 la_d[4] m5 reserved d21 la_d[47] b3 la_d[3] n4 reserved e21 la_d[46] c3 la_d[2] n5 reserved a18 la_d[45] b2 la_d[1] g3 reserved b18 la_d[44] c2 la_d[0] h1 reserved c18 la_d[43] c14 la_a[20] h2 reserved a17 la_d[42] a13 la_a[19] h3 reserved b17 la_d[41] b13 la_a[18] j1 reserved c17 la_d[40] c13 la_a[17] j2 reserved a16 la_d[39] a12 la_a[16] j3 reserved b16 la_d[38] b12 la_a[15] k1 reserved c16 la_d[37] c12 la_a[14] k2 reserved a15 la_d[36] a11 la_a[13] k3 reserved b15 la_d[35] b11 la_a[12] l1 reserved c15 la_d[34] c11 la_a[11] l2 reserved a14 la_d[33] d11 la_a[10] l3 reserved b14 la_d[32] e11 la_a[9] m1 reserved d9 la_d[31] a10 la_a[8] m2 reserved e9 la_d[30] b10 la_a[7] m3 reserved d8 la_d[29] d10 la_a[6] u4 reserved e8 la_d[28] e10 la_a[5] u5 reserved d7 la_d[27] a8 la_a[4] v4 reserved e7 la_d[26] c7 la_a[3] v5 reserved d6 la_d[25] b8 la_dsc# w4 reserved e6 la_d[24] c1 la_clk w5 reserved d5 la_d[23] c9 la_we# y4 reserved e5 la_d[22] d12 la_we0# y5 reserved d4 la_d[21] e12 la_we1# aa4 reserved e4 la_d[20] c8 la_oe# aa5 reserved ab4 reserved u2 reserved ah7 m[4]_rxd[0] ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 77 zarlink semiconductor inc. ab5 reserved r28 mdc ae6 m[3]_rxd[0] ac4 reserved p28 mdio ah5 m[2]_rxd[0] ac5 reserved r29 m_clk ah2 m[1]_rxd[0] ad4 reserved ac29 reserved af2 m[0]_rxd[0] ad5 reserved ae28 reserved ac27 reserved w1 reserved aj27 reserved af29 reserved y1 reserved af27 reserved ag27 reserved y2 reserved aj25 reserved af26 reserved y3 reserved af24 reserved ag25 reserved aa1 reserved ah23 reserved ag23 reserved aa2 reserved ae19 reserved af23 reserved aa3 reserved af21 m[15]_rxd[1] ag21 reserved ab1 reserved aj19 m[14]_rxd[1] ah21 m[15]_crs_dv ab2 reserved af18 m[13]_rxd[1] af19 m[14]_crs_dv ab3 reserved aj17 m[12]_rxd[1] af17 m[13]_crs_dv ac1 reserved aj15 m[11]_rxd[1] ag17 m[12]_crs_dv ac2 reserved af15 m[10]_rxd[1] ag15 m[11]_crs_dv ac3 reserved aj13 m[9]_rxd [1] af14 m[10]_crs_dv ad1 reserved af12 m[8]_rxd [1] ag13 m[9 ]_crs_dv ad2 reserved aj11 m[7]_rxd [1] af11 m[8]_crs_dv ad3 reserved aj9 m[6]_rxd[ 1] ag11 m[7]_crs_dv n3 reserved af9 m[5]_rxd[1] ag9 m[6]_crs_dv n2 reserved aj7 m[4]_rxd[1] af8 m[5]_crs_dv n1 reserved af6 m[3]_rxd[1] ag7 m[4]_crs_dv p3 reserved aj5 m[2]_rxd[1] af5 m[3]_crs_dv p2 reserved aj3 m[1]_rxd[1] ag5 m[2]_crs_dv p1 reserved af1 m[0]_rxd[1] ah3 m[1]_crs_dv r5 reserved ac28 reserved af3 m[0]_crs_dv r4 reserved af28 reserved ad29 reserved r3 reserved ah27 reserved ag28 reserved r2 reserved ae27 reserved aj26 reserved ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 78 zarlink semiconductor inc. r1 reserved ah25 reserved ae26 reserved t5 reserved ae24 reserved aj24 reserved t4 reserved af22 reserved ae23 reserved t3 reserved af20 reserved aj22 reserved t2 reserved ae21 m[15]_rxd[0] aj20 reserved t1 reserved ah19 m[14]_ rxd[0] ae20 m[15]_txen w3 reserved ah20 m[13]_rxd[0] aj18 m[14]_txen w2 reserved ah17 m[12]_rxd[0] aj21 m[13]_txen v1 reserved ah15 m[11]_rxd[0] aj16 m[12]_txen g1 reserved ae15 m[10]_rxd[0] aj14 m[11]_txen v3 reserved ah13 m[9]_r xd[0] ae14 m[10]_txen p4 reserved ae12 m[8]_rx d[0] aj12 m[9]_txen p5 reserved ah11 m[7]_rxd[0] ae11 m[8]_txen v2 reserved ah9 m[6]_rxd[0] aj10 m[7]_txen u1 reserved ae9 m[5]_rxd[0] aj8 m[6]_txen ae8 m[5]_txen ah8 m[6]_txd[0] g27 reserved aj6 m[4]_txen af7 m[5]_txd[0] h29 reserved ae5 m[3]_txen ah6 m[4]_txd[0] h28 reserved aj4 m[2]_txen af4 m[3]_txd[0] h27 reserved ag1 m[1]_txen ah4 m[2]_txd[0] j29 reserved ae1 m[0]_txen ag2 m[1]_txd[0] j28 reserved ad27 reserved ae2 m[0]_txd[0] j27 reserved ah28 reserved u26 reserved k29 reserved ag26 reserved u25 reserved k28 reserved ae25 reserved v26 reserved k27 reserved ag24 reserved v25 reserved l29 reserved ae22 reserved w26 reserved l28 reserved aj23 reserved w25 reserved l27 reserved ag20 reserved y27 reserved m29 reserved ae18 m[15]_txd[1] y26 reserved m28 reserved ag18 m[14]_txd[1] aa26 reserved m27 reserved ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 79 zarlink semiconductor inc. ae16 m[13]_txd[1] aa25 reserved g26 reserved ag16 m[12]_txd[1] ab26 reserved g25 reserved ag14 m[11]_txd[1] ab25 reserved h26 reserved ae13 m[10]_txd[1] ac26 reserved h25 reserved ag12 m[9]_txd[1] ac25 reserved j26 reserved ae10 m[8]_txd[1] ad26 reserved j25 reserved ag10 m[7]_txd[1] ad25 reserved k25 reserved ag8 m[6]_txd[1] u27 reserved k26 reserved ae7 m[5]_txd[1] v29 reserved m25 reserved ag6 m[4]_txd[1] v28 reserved l26 reserved ae4 m[3]_txd[1] v27 reserved m26 reserved ag4 m[2]_txd[1] w29 reserved l25 reserved ag3 m[1]_txd[1] w28 reserved n26 reserved ae3 m[0]_txd[1] w27 reserved n25 reserved ad28 reserved y29 reserved p26 reserved ag29 reserved y28 reserved p25 reserved ah26 reserved y25 reserved f28 reserved af25 reserved aa29 reserved g28 reserved ah24 reserved aa28 reserved e25 reserved ag22 reserved aa27 reserved g29 reserved ah22 reserved ab29 reserved f29 reserved ae17 reserved ab28 reserved f26 reserved ag19 m[15]_txd[0] ab27 reserved e26 reserved ah18 m[14]_txd[0] r26 reserved f25 reserved af16 m[13]_txd[0] t25 reserved e24 bist_done/tstout[15] ah16 m[12]_txd[0] t26 reserved d24 bist_in_prc/tst0ut[14] ah14 m[11]_txd[0] t28 reserved d25 mct_err/tstout[13] af13 m[10]_txd[0] u28 reserved d26 fcb_err/tstout[12] ah12 m[9]_txd[0] r25 reserved c26 checksum_ok/tstout[11] af10 m[8]_txd[0] u29 reserved d27 init_start/tstout[10] ah10 m[7]_txd[0] t29 reserved c27 init_done/tstout[9] ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 80 zarlink semiconductor inc. b27 tstout[8] u18 vss n12 vss a27 tstout[7] v12 vss n13 vss e28 tstout[6] v13 vss k17 vdd d28 tstout[5] v14 vss k18 vdd c28 tstout[4] v15 vss m10 vdd b28 tstout[3] v16 vss n10 vdd e29 led_bit/tstout[2] v17 vss m20 vdd d29 led_syn/tstout[1] v18 vss n20 vdd c29 led_clk/tstout[0] n14 vss u10 vdd n29 reserved n15 vss v10 vdd p29 reserved n16 vss u20 vdd f3 scan_en n17 vss v20 vdd e1 sclk n18 vss y12 vdd u3 t_mode0 p12 vss y13 vdd c10 t_mode1 p13 vss y17 vdd b24 reserved p14 vss y18 vdd a21 trunk1 p15 vss k12 vdd c22 trunk0 p16 vss k13 vdd a26 strobe c19 oe_clk2 m16 vss b26 d0 b19 oe_clk1 m17 vss c25 autofd a19 oe_clk0 m18 vss a24 scl r13 vss f16 vdd33 a25 sda r14 vss f17 vdd33 f1 avcc r15 vss n6 vdd33 d1 agnd r16 vss p6 vdd33 d22 scancol r17 vss r6 vdd33 e23 scanlink r18 vss t6 vdd33 e27 scanmode t12 vss u6 vdd33 n28 t13 vss n24 vdd33 n27 t14 vss p24 vdd33 f2 resin# t15 vss r24 vdd33 ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 81 zarlink semiconductor inc. 13.4 ac/dc timing 13.4.1 absolute maximum ratings storage temperature -65c to +150c operating temperature -40c to 85c maximum junction temperature +125c supply voltage vcc with respect to v ss +3.0 v to +3.6 v supply voltage vdd with respect to v ss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vdd33 + 0.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functionality at or ab ove these limits is not implied. 13.4.2 dc electrical characteristics vcc = 3.0v to 3.6v (3.3v +/- 10%)t ambient = -40c to 85c vdd = 2.5 v +10% - 5% g2 resetout# t16 vss t24 vdd33 b22 reserved t17 vss u24 vdd33 a22 reserved t18 vss ad13 vdd33 c23 reserved u12 vss ad14 vdd33 b23 reserved u13 vss ad15 vdd33 a23 reserved u14 vss ad16 vdd33 c24 reserved u15 vss ad17 vdd33 d23 scanclk u16 vss f13 vdd33 t27 reserved u17 vss f14 vdd33 f27 reserved m12 vss f15 vdd33 c20 la_clk2 m13 vss b20 la_clk1 m14 vss a20 la_clk0 m15 vss c21 p_d p17 vss e20 reserved p18 vss b25 reserved r12 vss ball no. signal name ball no. signal name ball no. signal name ZL50415 data sheet 82 zarlink semiconductor inc. 13.4.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation ( -50) 100 mhz i cc supply current ? @ 100 mhz (vcc=3.3 v) 250 ma i dd supply current ? @ 100 mhz (vdd=2.5 v) 1350 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vcc) (all pins except those with internal pull-up/pull-down resistors) 10 a i ol output leakage current (0.1 v < vout < vcc) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 10.2 c/w ja thermal resistance with 2 m/s air flow 8.9 c/w jc thermal resistance between junction and case 3.1 c/w jb thermal resistance between junction and board 6.6 c/w ZL50415 data sheet 83 zarlink semiconductor inc. 13.4.4 typical reset & bootstrap timing diagram figure 12 - typical reset & bootstrap timing diagram symbol parameter min typ note: r1 delay until resetout# is tri-stated 10 ns resetout# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of resin# a a. the tstout[8:0] pins will switch over to the led inte rface functionality in 3 sclk cycles after resin# goes high. r3 resetout# assertion 2 ms table 10 - reset & bootstrap timing resetout# tri-stated resin# r1 r2 r3 bootstrap pins inputs outputs outputs ZL50415 data sheet 84 zarlink semiconductor inc. 13.5 local frame buff er sbram memory interface 13.5.1 local sbram memory interface figure 13 - local memory interface ? input setup and hold timing figure 14 - local memory interface - output valid delay timing l1 l2 la_clk la_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l7-min l7-max l8-min l8-max la_clk la_d[63:0] la_a[20:3] la_adsc# la_we[1:0]# #### la_oe[1:0]# l9-min l9-max la_we# l10-min l10-max la_oe# ZL50415 data sheet 85 zarlink semiconductor inc. -100 mhz symbol parameter min. (ns) max. (ns) note: l1 la_d[63:0] input set-up time 4 l2 la_d[63:0] input hold time 1.5 l3 la_d[63:0] output valid delay 1.5 7 c l = 25 pf l4 la_a[20:3] output valid delay 2 7 c l = 30 pf l6 la_adsc# output valid delay 1 7 c l = 30 pf l7 la_we[1:0]#output valid delay 1 7 c l = 25 pf l8 la_oe[1:0]# output valid delay -1 1 c l = 25 pf l9 la_we# output valid delay 1 7 c l = 25 pf l10 la_oe# output valid delay 1 5 c l = 25 pf table 11 - ac characteristics ? local frame buffer sbram memory interface ZL50415 data sheet 86 zarlink semiconductor inc. 13.6 ac characteristics 13.6.1 reduced media independent interface figure 15 - ac characteristics ? reduced media independent interface figure 16 - ac characteristics ? reduced media independent interface table 12 - ac characteristics ? reduced media independent interface -50 mhz symbol parameter min. (ns) max. (ns) note: m2 m[15:0]_rxd[1:0] input setup time 4 m3 m[15:0]_rxd[1:0] input hold time 1 m4 m[15:0]_crs_dv input setup time 4 m5 m[15:0]_crs_dv input hold time 1 m6 m[15:0]_txen output delay time 2 11 c l = 20 pf m7 m[15:0]_txd[1:0] output delay time 2 11 c l = 20 pf m6-min m6-max m7-min m7-max m_clki m[15:0]_txen m[15:0] _txd[1:0] m2 m_clki m[15:0]_rxd m[15:0]_crs_dv m3 m4 m5 ZL50415 data sheet 87 zarlink semiconductor inc. 13.6.2 led interface figure 17 - ac characteristics ? led interface table 13 - ac characteristics ? led interface 13.6.3 scanlink scancol output delay timing figure 18 - scanlink scancol output delay timing figure 19 - scanlink, scancol setup timing variable freq. symbol parameter min. (ns) max. (ns) note: le5 led_syn output valid delay -1 7 c l = 30 pf le6 led_bit output valid delay -1 7 c l = 30 pf le5-min le5-max le6-min le6-max led_clk led_syn led_bit c5-min c5-max c7-min c7-max scanclk scanlink scancol scanclk c1 c2 scanlink c3 c4 scancol ZL50415 data sheet 88 zarlink semiconductor inc. table 14 - scanlink, scancol timing 13.6.4 mdio input setup and hold timing figure 20 - mdio input setup and hold timing figure 21 - mdio output delay timing table 15 - mdio timing -25 mhz symbol parameter min. (ns) max. (ns) note: c1 scanlink input set-up time 20 c2 scanlink input hold time 2 c3 scancol input setup time 20 c4 scancol input hold time 1 c5 scanlink output valid delay 0 10 c l = 30 pf c7 scancol output valid delay 0 10 c l = 30 pf 1mhz symbol parameter min. (ns) max. (ns) note: d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50 pf mdc d1 d2 mdio d3-min d3-max mdc mdio ZL50415 data sheet 89 zarlink semiconductor inc. 13.6.5 i 2 c input setup timing figure 22 - i 2 c input setup timing figure 23 - i 2 c output delay timing table 16 - i 2 c timing 50 khz symbol parameter min. (ns) max. (ns) note: s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 4 usec 6 usec c l = 30 pf * open drain output. low to high transistor is controlled by external pullup resistor. s1 s2 scl sd a s3-min s3-max scl sd a ZL50415 data sheet 90 zarlink semiconductor inc. 13.6.6 serial interface setup timing figure 24 - serial interface setup timing figure 25 - serial interface output delay timing table 17 - serial interface timing symbol parameter min. (ns) max. (ns) note: d1 d0 setup time 20 d2 d0 hold time 3 s d3 autofd output delay time 1 50 c l = 100 pf d4 strobe low time 5 s d5 strobe high time 5 s strobe d1 d2 d0 d1 d2 d4 d5 d3-min d3-max strobe autofd apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 2.20 e e b e1 dimension d d1 a2 a1 a 1.27 553 max 0.70 2.46 1.17 ref 0.50 min 3. seating plane is defined by the spherical crowns of the solder balls. 1. controlling dimensions are in mm 2. dimension "b" is measured at the maximum solder ball diameter 4. n is the number of solder balls 5. not to scale. note: 0.60 0.90 37.30 37.70 34.50 ref 37.30 37.70 34.50 ref e1 d1 d e e b a2 6. substrate thickness is 0.56 mm www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
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